include/configs/ls1046afrwy.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019-2020 NXP
   4  */
   5
   6 #ifndef __LS1046AFRWY_H__
   7 #define __LS1046AFRWY_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
  14 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
  15
  16 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  17
  18 /*
  19  * NAND Flash Definitions
  20  */
  21
  22 #define CONFIG_SYS_NAND_BASE            0x7e800000
  23 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  24
  25 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  26 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  27                                 | CSPR_PORT_SIZE_8      \
  28                                 | CSPR_MSEL_NAND        \
  29                                 | CSPR_V)
  30 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  31 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  32                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  33                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  34                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  35                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  36                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
  37                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  38
  39 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  40                                         FTIM0_NAND_TWP(0x18)   | \
  41                                         FTIM0_NAND_TWCHT(0x7) | \
  42                                         FTIM0_NAND_TWH(0xa))
  43 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  44                                         FTIM1_NAND_TWBE(0x39)  | \
  45                                         FTIM1_NAND_TRR(0xe)   | \
  46                                         FTIM1_NAND_TRP(0x18))
  47 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  48                                         FTIM2_NAND_TREH(0xa) | \
  49                                         FTIM2_NAND_TWHRE(0x1e))
  50 #define CONFIG_SYS_NAND_FTIM3           0x0
  51
  52 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  53 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  54 #define CONFIG_MTD_NAND_VERIFY_WRITE
  55
  56 /* IFC Timing Params */
  57 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
  58 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
  59 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
  60 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
  61 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
  62 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
  63 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
  64 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
  65
  66 /* EEPROM */
  67 #define CONFIG_SYS_I2C_EEPROM_NXID
  68 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  69 #define I2C_RETIMER_ADDR                        0x18
  70
  71 /* I2C bus multiplexer */
  72 #define I2C_MUX_PCA_ADDR_PRI                    0x77 /* Primary Mux*/
  73 #define I2C_MUX_CH_DEFAULT                      0x1 /* Channel 0*/
  74 #define I2C_MUX_CH_RTC                          0x1 /* Channel 0*/
  75
  76 /* RTC */
  77 #define RTC
  78 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 0 I2C bus 0*/
  79 #define CONFIG_SYS_RTC_BUS_NUM                  0
  80
  81 /*
  82  * Environment
  83  */
  84 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
  85
  86 #ifndef CONFIG_SPL_BUILD
  87 #undef BOOT_TARGET_DEVICES
  88 #define BOOT_TARGET_DEVICES(func) \
  89         func(MMC, mmc, 0) \
  90         func(USB, usb, 0) \
  91         func(DHCP, dhcp, na)
  92 #endif
  93
  94 /* FMan */
  95 #ifdef CONFIG_SYS_DPAA_FMAN
  96
  97 #define QSGMII_PORT1_PHY_ADDR           0x1c
  98 #define QSGMII_PORT2_PHY_ADDR           0x1d
  99 #define QSGMII_PORT3_PHY_ADDR           0x1e
 100 #define QSGMII_PORT4_PHY_ADDR           0x1f
 101
 102 #define FDT_SEQ_MACADDR_FROM_ENV
 103
 104 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 105
 106 #endif
 107
 108 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 109                            "env exists secureboot && esbc_halt;;"
 110 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 111                            "env exists secureboot && esbc_halt;"
 112
 113 #include <asm/fsl_secure_boot.h>
 114
 115 #endif /* __LS1046AFRWY_H__ */