include/configs/ls1046a_common.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1046A_COMMON_H
   8 #define __LS1046A_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_MP
  13 #define CONFIG_SYS_FSL_CLK
  14 #define CONFIG_GICV2
  15
  16 #include <asm/arch/config.h>
  17 #ifdef CONFIG_SYS_FSL_SRDS_1
  18 #define CONFIG_SYS_HAS_SERDES
  19 #endif
  20
  21 /* Link Definitions */
  22 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  23
  24 #define CONFIG_SUPPORT_RAW_INITRD
  25
  26 #define CONFIG_SKIP_LOWLEVEL_INIT
  27 #define CONFIG_BOARD_EARLY_INIT_F       1
  28
  29 #define CONFIG_VERY_BIG_RAM
  30 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  31 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  32 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  33 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  34
  35 #define CPU_RELEASE_ADDR               secondary_boot_func
  36
  37 /* Generic Timer Definitions */
  38 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  39
  40 /* Size of malloc() pool */
  41 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  42
  43 /* Serial Port */
  44 #define CONFIG_CONS_INDEX               1
  45 #define CONFIG_SYS_NS16550_SERIAL
  46 #define CONFIG_SYS_NS16550_REG_SIZE     1
  47 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
  48
  49 #define CONFIG_BAUDRATE                 115200
  50 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  51
  52 /* SD boot SPL */
  53 #ifdef CONFIG_SD_BOOT
  54 #define CONFIG_SPL_FRAMEWORK
  55 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  56 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  57 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  58 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  59 #define CONFIG_SPL_ENV_SUPPORT
  60 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  61 #define CONFIG_SPL_WATCHDOG_SUPPORT
  62 #define CONFIG_SPL_I2C_SUPPORT
  63 #define CONFIG_SPL_SERIAL_SUPPORT
  64 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  65
  66 #define CONFIG_SPL_MMC_SUPPORT
  67 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x110
  68 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x500
  69 #define CONFIG_SPL_TEXT_BASE            0x10000000
  70 #define CONFIG_SPL_MAX_SIZE             0x1f000         /* 124 KiB */
  71 #define CONFIG_SPL_STACK                0x10020000
  72 #define CONFIG_SPL_PAD_TO               0x21000         /* 132 KiB */
  73 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  74 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  75 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  76                                         CONFIG_SPL_BSS_MAX_SIZE)
  77 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  78 #define CONFIG_SYS_MONITOR_LEN          0xa0000
  79 #endif
  80
  81 /* NAND SPL */
  82 #ifdef CONFIG_NAND_BOOT
  83 #define CONFIG_SPL_PBL_PAD
  84 #define CONFIG_SPL_FRAMEWORK
  85 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  86 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  87 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  88 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  89 #define CONFIG_SPL_ENV_SUPPORT
  90 #define CONFIG_SPL_WATCHDOG_SUPPORT
  91 #define CONFIG_SPL_I2C_SUPPORT
  92 #define CONFIG_SPL_SERIAL_SUPPORT
  93 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  94
  95 #define CONFIG_SPL_NAND_SUPPORT
  96 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  97 #define CONFIG_SPL_TEXT_BASE            0x10000000
  98 #define CONFIG_SPL_MAX_SIZE             0x1d000         /* 116 KiB */
  99 #define CONFIG_SPL_STACK                0x1001f000
 100 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 101 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 102
 103 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
 104 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 105 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
 106                                         CONFIG_SPL_BSS_MAX_SIZE)
 107 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 108 #define CONFIG_SYS_MONITOR_LEN          0xa0000
 109 #endif
 110
 111 /* I2C */
 112 #define CONFIG_SYS_I2C
 113 #define CONFIG_SYS_I2C_MXC
 114 #define CONFIG_SYS_I2C_MXC_I2C1
 115 #define CONFIG_SYS_I2C_MXC_I2C2
 116 #define CONFIG_SYS_I2C_MXC_I2C3
 117 #define CONFIG_SYS_I2C_MXC_I2C4
 118
 119 /* Command line configuration */
 120 #define CONFIG_CMD_ENV
 121
 122 /* MMC */
 123 #define CONFIG_MMC
 124 #ifdef CONFIG_MMC
 125 #define CONFIG_FSL_ESDHC
 126 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 127 #define CONFIG_GENERIC_MMC
 128 #define CONFIG_DOS_PARTITION
 129 #endif
 130
 131 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 132
 133 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 134
 135 /* FMan ucode */
 136 #define CONFIG_SYS_DPAA_FMAN
 137 #ifdef CONFIG_SYS_DPAA_FMAN
 138 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 139
 140 #ifdef CONFIG_SD_BOOT
 141 /*
 142  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 143  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 144  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 145  */
 146 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 147 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 148 #elif defined(CONFIG_QSPI_BOOT)
 149 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 150 #define CONFIG_SYS_FMAN_FW_ADDR         0x40300000
 151 #define CONFIG_ENV_SPI_BUS              0
 152 #define CONFIG_ENV_SPI_CS               0
 153 #define CONFIG_ENV_SPI_MAX_HZ           1000000
 154 #define CONFIG_ENV_SPI_MODE             0x03
 155 #elif defined(CONFIG_NAND_BOOT)
 156 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 157 #define CONFIG_SYS_FMAN_FW_ADDR         (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 158 #else
 159 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 160 #define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 161 #endif
 162 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 163 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 164 #endif
 165
 166 /* Miscellaneous configurable options */
 167 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 168 #define CONFIG_ARCH_EARLY_INIT_R
 169 #define CONFIG_BOARD_LATE_INIT
 170
 171 #define CONFIG_HWCONFIG
 172 #define HWCONFIG_BUFFER_SIZE            128
 173
 174 /* Initial environment variables */
 175 #define CONFIG_EXTRA_ENV_SETTINGS               \
 176         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 177         "loadaddr=0x80100000\0"                 \
 178         "ramdisk_addr=0x800000\0"               \
 179         "ramdisk_size=0x2000000\0"              \
 180         "fdt_high=0xffffffffffffffff\0"         \
 181         "initrd_high=0xffffffffffffffff\0"      \
 182         "kernel_start=0x1000000\0"              \
 183         "kernel_load=0xa0000000\0"              \
 184         "kernel_size=0x2800000\0"               \
 185         "console=ttyS0,115200\0"                \
 186                 MTDPARTS_DEFAULT "\0"
 187
 188 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 189                                         "earlycon=uart8250,mmio,0x21c0500 " \
 190                                         MTDPARTS_DEFAULT
 191 /* Monitor Command Prompt */
 192 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 193 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 194                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 195 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 196 #define CONFIG_SYS_LONGHELP
 197 #define CONFIG_CMDLINE_EDITING          1
 198 #define CONFIG_AUTO_COMPLETE
 199 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 200
 201 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 202
 203 /* Hash command with SHA acceleration supported in hardware */
 204 #ifdef CONFIG_FSL_CAAM
 205 #define CONFIG_CMD_HASH
 206 #define CONFIG_SHA_HW_ACCEL
 207 #endif
 208
 209 #endif /* __LS1046A_COMMON_H */