armv8: ls1046ardb: Add LS1046ARDB board support
[platform/kernel/u-boot.git] / include / configs / ls1046a_common.h
1 /*
2  * Copyright 2016 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
9
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_FSL_LSCH2
13 #define CONFIG_LS1046A
14 #define CONFIG_MP
15 #define CONFIG_SYS_FSL_CLK
16 #define CONFIG_GICV2
17
18 #include <asm/arch/config.h>
19 #ifdef CONFIG_SYS_FSL_SRDS_1
20 #define CONFIG_SYS_HAS_SERDES
21 #endif
22
23 /* Link Definitions */
24 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
25
26 #define CONFIG_SUPPORT_RAW_INITRD
27
28 #define CONFIG_SKIP_LOWLEVEL_INIT
29 #define CONFIG_BOARD_EARLY_INIT_F       1
30
31 #define CONFIG_VERY_BIG_RAM
32 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
33 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
34 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
35 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
36
37 #define CPU_RELEASE_ADDR               secondary_boot_func
38
39 /* Generic Timer Definitions */
40 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
41
42 /* Size of malloc() pool */
43 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
44
45 /* Serial Port */
46 #define CONFIG_CONS_INDEX               1
47 #define CONFIG_SYS_NS16550_SERIAL
48 #define CONFIG_SYS_NS16550_REG_SIZE     1
49 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
50
51 #define CONFIG_BAUDRATE                 115200
52 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
53
54 /* SD boot SPL */
55 #ifdef CONFIG_SD_BOOT
56 #define CONFIG_SPL_FRAMEWORK
57 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
58 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
59 #define CONFIG_SPL_LIBCOMMON_SUPPORT
60 #define CONFIG_SPL_LIBGENERIC_SUPPORT
61 #define CONFIG_SPL_ENV_SUPPORT
62 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
63 #define CONFIG_SPL_WATCHDOG_SUPPORT
64 #define CONFIG_SPL_I2C_SUPPORT
65 #define CONFIG_SPL_SERIAL_SUPPORT
66 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
67
68 #define CONFIG_SPL_MMC_SUPPORT
69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x110
70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x500
71 #define CONFIG_SPL_TEXT_BASE            0x10000000
72 #define CONFIG_SPL_MAX_SIZE             0x1f000         /* 124 KiB */
73 #define CONFIG_SPL_STACK                0x10020000
74 #define CONFIG_SPL_PAD_TO               0x21000         /* 132 KiB */
75 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
76 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
77 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
78                                         CONFIG_SPL_BSS_MAX_SIZE)
79 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
80 #define CONFIG_SYS_MONITOR_LEN          0xa0000
81 #endif
82
83 /* I2C */
84 #define CONFIG_SYS_I2C
85 #define CONFIG_SYS_I2C_MXC
86 #define CONFIG_SYS_I2C_MXC_I2C1
87 #define CONFIG_SYS_I2C_MXC_I2C2
88 #define CONFIG_SYS_I2C_MXC_I2C3
89 #define CONFIG_SYS_I2C_MXC_I2C4
90
91 /* Command line configuration */
92 #define CONFIG_CMD_ENV
93
94 /* MMC */
95 #define CONFIG_MMC
96 #ifdef CONFIG_MMC
97 #define CONFIG_FSL_ESDHC
98 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
99 #define CONFIG_GENERIC_MMC
100 #define CONFIG_DOS_PARTITION
101 #endif
102
103 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
104
105 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
106
107 /* FMan ucode */
108 #define CONFIG_SYS_DPAA_FMAN
109 #ifdef CONFIG_SYS_DPAA_FMAN
110 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
111
112 #ifdef CONFIG_SD_BOOT
113 /*
114  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
115  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
116  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
117  */
118 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
119 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
120 #else
121 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
122 #define CONFIG_SYS_FMAN_FW_ADDR         0x40300000
123 #define CONFIG_ENV_SPI_BUS              0
124 #define CONFIG_ENV_SPI_CS               0
125 #define CONFIG_ENV_SPI_MAX_HZ           1000000
126 #define CONFIG_ENV_SPI_MODE             0x03
127 #endif
128 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
129 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
130 #endif
131
132 /* Miscellaneous configurable options */
133 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
134 #define CONFIG_ARCH_EARLY_INIT_R
135 #define CONFIG_BOARD_LATE_INIT
136
137 #define CONFIG_HWCONFIG
138 #define HWCONFIG_BUFFER_SIZE            128
139
140 /* Initial environment variables */
141 #define CONFIG_EXTRA_ENV_SETTINGS               \
142         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
143         "loadaddr=0x80100000\0"                 \
144         "ramdisk_addr=0x800000\0"               \
145         "ramdisk_size=0x2000000\0"              \
146         "fdt_high=0xffffffffffffffff\0"         \
147         "initrd_high=0xffffffffffffffff\0"      \
148         "kernel_start=0x1000000\0"              \
149         "kernel_load=0xa0000000\0"              \
150         "kernel_size=0x2800000\0"               \
151         "console=ttyS0,115200\0"                \
152                 MTDPARTS_DEFAULT "\0"
153
154 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
155                                         "earlycon=uart8250,mmio,0x21c0500 " \
156                                         MTDPARTS_DEFAULT
157 /* Monitor Command Prompt */
158 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
159 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
160                                         sizeof(CONFIG_SYS_PROMPT) + 16)
161 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
162 #define CONFIG_SYS_LONGHELP
163 #define CONFIG_CMDLINE_EDITING          1
164 #define CONFIG_AUTO_COMPLETE
165 #define CONFIG_SYS_MAXARGS              64      /* max command args */
166
167 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
168
169 /* Hash command with SHA acceleration supported in hardware */
170 #ifdef CONFIG_FSL_CAAM
171 #define CONFIG_CMD_HASH
172 #define CONFIG_SHA_HW_ACCEL
173 #endif
174
175 #endif /* __LS1046A_COMMON_H */