1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
20 #if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
24 #if defined(CONFIG_SPL_BUILD) && \
25 !defined(CONFIG_SPL_FSL_LS_PPA)
29 #define CONFIG_REMAKE_ELF
32 #include <asm/arch/config.h>
33 #include <asm/arch/stream_id_lsch2.h>
35 /* Link Definitions */
37 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
42 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_VERY_BIG_RAM
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
50 #define CPU_RELEASE_ADDR secondary_boot_addr
52 /* Generic Timer Definitions */
53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
55 /* Size of malloc() pool */
56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
59 #define CONFIG_SYS_NS16550_SERIAL
60 #define CONFIG_SYS_NS16550_REG_SIZE 1
61 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
68 #define CONFIG_SPL_STACK 0x10020000
69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
73 CONFIG_SPL_BSS_MAX_SIZE)
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
76 #ifdef CONFIG_NXP_ESBC
77 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
79 * HDR would be appended at end of image and copied to DDR along
80 * with U-Boot image. Here u-boot max. size is 512K. So if binary
81 * size increases then increase this size in case of secure boot as
82 * it uses raw u-boot image instead of fit image.
84 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
86 #define CONFIG_SYS_MONITOR_LEN 0x100000
87 #endif /* ifdef CONFIG_NXP_ESBC */
90 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
91 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
92 #define CONFIG_SPL_MAX_SIZE 0x1f000
93 #define CONFIG_SPL_STACK 0x10020000
94 #define CONFIG_SPL_PAD_TO 0x20000
95 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
96 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
97 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
98 CONFIG_SPL_BSS_MAX_SIZE)
99 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
100 #define CONFIG_SYS_MONITOR_LEN 0x100000
104 #ifdef CONFIG_NAND_BOOT
105 #define CONFIG_SPL_PBL_PAD
106 #define CONFIG_SPL_LIBCOMMON_SUPPORT
107 #define CONFIG_SPL_LIBGENERIC_SUPPORT
108 #define CONFIG_SPL_ENV_SUPPORT
109 #define CONFIG_SPL_WATCHDOG
110 #define CONFIG_SPL_I2C
111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
113 #define CONFIG_SPL_NAND_SUPPORT
114 #define CONFIG_SPL_DRIVERS_MISC
115 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
116 #define CONFIG_SPL_STACK 0x1001f000
117 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
118 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
120 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
121 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
122 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
123 CONFIG_SPL_BSS_MAX_SIZE)
124 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
125 #define CONFIG_SYS_MONITOR_LEN 0xa0000
129 #ifdef CONFIG_DM_GPIO
130 #ifndef CONFIG_MPC8XXX_GPIO
131 #define CONFIG_MPC8XXX_GPIO
136 #if !CONFIG_IS_ENABLED(DM_I2C)
137 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
138 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
139 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
140 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
142 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
143 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
147 #define CONFIG_PCIE1 /* PCIE controller 1 */
148 #define CONFIG_PCIE2 /* PCIE controller 2 */
149 #define CONFIG_PCIE3 /* PCIE controller 3 */
152 #define CONFIG_PCI_SCAN_SHOW
157 #define CONFIG_SCSI_AHCI_PLAT
159 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
161 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
162 #define CONFIG_SYS_SCSI_MAX_LUN 1
163 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
164 CONFIG_SYS_SCSI_MAX_LUN)
169 #define CONFIG_SYS_DPAA_FMAN
170 #ifdef CONFIG_SYS_DPAA_FMAN
171 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
174 #ifdef CONFIG_TFABOOT
175 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
177 #ifdef CONFIG_SD_BOOT
179 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
180 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
181 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
183 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
184 #elif defined(CONFIG_QSPI_BOOT)
185 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
186 #elif defined(CONFIG_NAND_BOOT)
187 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
189 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
192 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
193 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
196 /* Miscellaneous configurable options */
197 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
199 #define CONFIG_HWCONFIG
200 #define HWCONFIG_BUFFER_SIZE 128
202 #ifndef CONFIG_SPL_BUILD
203 #define BOOT_TARGET_DEVICES(func) \
204 func(SCSI, scsi, 0) \
208 #include <config_distro_bootcmd.h>
211 #if defined(CONFIG_TARGET_LS1046AFRWY)
212 #define LS1046A_BOOT_SRC_AND_HDR\
213 "boot_scripts=ls1046afrwy_boot.scr\0" \
214 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
215 #elif defined(CONFIG_TARGET_LS1046AQDS)
216 #define LS1046A_BOOT_SRC_AND_HDR\
217 "boot_scripts=ls1046aqds_boot.scr\0" \
218 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
220 #define LS1046A_BOOT_SRC_AND_HDR\
221 "boot_scripts=ls1046ardb_boot.scr\0" \
222 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
225 /* Initial environment variables */
226 #define CONFIG_EXTRA_ENV_SETTINGS \
227 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
228 "ramdisk_addr=0x800000\0" \
229 "ramdisk_size=0x2000000\0" \
230 "bootm_size=0x10000000\0" \
231 "fdt_addr=0x64f00000\0" \
232 "kernel_addr=0x61000000\0" \
233 "scriptaddr=0x80000000\0" \
234 "scripthdraddr=0x80080000\0" \
235 "fdtheader_addr_r=0x80100000\0" \
236 "kernelheader_addr_r=0x80200000\0" \
237 "load_addr=0xa0000000\0" \
238 "kernel_addr_r=0x81000000\0" \
239 "fdt_addr_r=0x90000000\0" \
240 "ramdisk_addr_r=0xa0000000\0" \
241 "kernel_start=0x1000000\0" \
242 "kernelheader_start=0x600000\0" \
243 "kernel_load=0xa0000000\0" \
244 "kernel_size=0x2800000\0" \
245 "kernelheader_size=0x40000\0" \
246 "kernel_addr_sd=0x8000\0" \
247 "kernel_size_sd=0x14000\0" \
248 "kernelhdr_addr_sd=0x3000\0" \
249 "kernelhdr_size_sd=0x10\0" \
250 "console=ttyS0,115200\0" \
251 CONFIG_MTDPARTS_DEFAULT "\0" \
253 LS1046A_BOOT_SRC_AND_HDR \
254 "scan_dev_for_boot_part=" \
255 "part list ${devtype} ${devnum} devplist; " \
256 "env exists devplist || setenv devplist 1; " \
257 "for distro_bootpart in ${devplist}; do " \
258 "if fstype ${devtype} " \
259 "${devnum}:${distro_bootpart} " \
260 "bootfstype; then " \
261 "run scan_dev_for_boot; " \
265 "load ${devtype} ${devnum}:${distro_bootpart} " \
266 "${scriptaddr} ${prefix}${script}; " \
267 "env exists secureboot && load ${devtype} " \
268 "${devnum}:${distro_bootpart} " \
269 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
270 "env exists secureboot " \
271 "&& esbc_validate ${scripthdraddr};" \
272 "source ${scriptaddr}\0" \
273 "qspi_bootcmd=echo Trying load from qspi..;" \
274 "sf probe && sf read $load_addr " \
275 "$kernel_start $kernel_size; env exists secureboot " \
276 "&& sf read $kernelheader_addr_r $kernelheader_start " \
277 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
278 "bootm $load_addr#$board\0" \
279 "nand_bootcmd=echo Trying load from nand..;" \
280 "nand info; nand read $load_addr " \
281 "$kernel_start $kernel_size; env exists secureboot " \
282 "&& nand read $kernelheader_addr_r $kernelheader_start " \
283 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
284 "bootm $load_addr#$board\0" \
285 "nor_bootcmd=echo Trying load from nor..;" \
286 "cp.b $kernel_addr $load_addr " \
287 "$kernel_size; env exists secureboot " \
288 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
289 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
290 "bootm $load_addr#$board\0" \
291 "sd_bootcmd=echo Trying load from SD ..;" \
292 "mmcinfo; mmc read $load_addr " \
293 "$kernel_addr_sd $kernel_size_sd && " \
294 "env exists secureboot && mmc read $kernelheader_addr_r " \
295 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
296 " && esbc_validate ${kernelheader_addr_r};" \
297 "bootm $load_addr#$board\0"
301 /* Monitor Command Prompt */
302 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
304 #define CONFIG_SYS_MAXARGS 64 /* max command args */
306 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
308 #include <asm/arch/soc.h>
310 #endif /* __LS1046A_COMMON_H */