1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
6 #ifndef __LS1046A_COMMON_H
7 #define __LS1046A_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
19 #if defined(CONFIG_SPL_BUILD) && \
20 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
23 #if defined(CONFIG_SPL_BUILD) && \
24 !defined(CONFIG_SPL_FSL_LS_PPA)
28 #define CONFIG_REMAKE_ELF
31 #include <asm/arch/config.h>
32 #include <asm/arch/stream_id_lsch2.h>
34 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
41 #define CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_VERY_BIG_RAM
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
49 #define CPU_RELEASE_ADDR secondary_boot_func
51 /* Generic Timer Definitions */
52 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
54 /* Size of malloc() pool */
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE 1
60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
66 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
67 #define CONFIG_SPL_STACK 0x10020000
68 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
69 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
70 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
72 CONFIG_SPL_BSS_MAX_SIZE)
73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75 #ifdef CONFIG_SECURE_BOOT
76 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
78 * HDR would be appended at end of image and copied to DDR along
79 * with U-Boot image. Here u-boot max. size is 512K. So if binary
80 * size increases then increase this size in case of secure boot as
81 * it uses raw u-boot image instead of fit image.
83 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85 #define CONFIG_SYS_MONITOR_LEN 0x100000
86 #endif /* ifdef CONFIG_SECURE_BOOT */
89 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
90 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
91 #define CONFIG_SPL_MAX_SIZE 0x1f000
92 #define CONFIG_SPL_STACK 0x10020000
93 #define CONFIG_SPL_PAD_TO 0x20000
94 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
95 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
96 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
97 CONFIG_SPL_BSS_MAX_SIZE)
98 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
99 #define CONFIG_SYS_MONITOR_LEN 0x100000
100 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
104 #ifdef CONFIG_NAND_BOOT
105 #define CONFIG_SPL_PBL_PAD
106 #define CONFIG_SPL_LIBCOMMON_SUPPORT
107 #define CONFIG_SPL_LIBGENERIC_SUPPORT
108 #define CONFIG_SPL_ENV_SUPPORT
109 #define CONFIG_SPL_WATCHDOG_SUPPORT
110 #define CONFIG_SPL_I2C_SUPPORT
111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
113 #define CONFIG_SPL_NAND_SUPPORT
114 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
115 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
116 #define CONFIG_SPL_STACK 0x1001f000
117 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
118 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
120 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
121 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
122 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
123 CONFIG_SPL_BSS_MAX_SIZE)
124 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
125 #define CONFIG_SYS_MONITOR_LEN 0xa0000
129 #define CONFIG_SYS_I2C
132 #define CONFIG_PCIE1 /* PCIE controller 1 */
133 #define CONFIG_PCIE2 /* PCIE controller 2 */
134 #define CONFIG_PCIE3 /* PCIE controller 3 */
137 #define CONFIG_PCI_SCAN_SHOW
142 #define CONFIG_SCSI_AHCI_PLAT
144 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
146 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
147 #define CONFIG_SYS_SCSI_MAX_LUN 1
148 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
149 CONFIG_SYS_SCSI_MAX_LUN)
152 /* Command line configuration */
157 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
163 #define CONFIG_SYS_DPAA_FMAN
164 #ifdef CONFIG_SYS_DPAA_FMAN
165 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
168 #ifdef CONFIG_TFABOOT
169 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
171 #ifdef CONFIG_SD_BOOT
173 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
174 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
175 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
177 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
178 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
179 #elif defined(CONFIG_QSPI_BOOT)
180 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
181 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
182 #elif defined(CONFIG_NAND_BOOT)
183 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
184 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
186 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
187 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
190 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
191 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
194 /* Miscellaneous configurable options */
195 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
197 #define CONFIG_HWCONFIG
198 #define HWCONFIG_BUFFER_SIZE 128
200 #ifndef CONFIG_SPL_BUILD
201 #define BOOT_TARGET_DEVICES(func) \
202 func(SCSI, scsi, 0) \
206 #include <config_distro_bootcmd.h>
210 /* Initial environment variables */
211 #define CONFIG_EXTRA_ENV_SETTINGS \
212 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
213 "ramdisk_addr=0x800000\0" \
214 "ramdisk_size=0x2000000\0" \
215 "fdt_high=0xffffffffffffffff\0" \
216 "initrd_high=0xffffffffffffffff\0" \
217 "fdt_addr=0x64f00000\0" \
218 "kernel_addr=0x65000000\0" \
219 "scriptaddr=0x80000000\0" \
220 "scripthdraddr=0x80080000\0" \
221 "fdtheader_addr_r=0x80100000\0" \
222 "kernelheader_addr_r=0x80200000\0" \
223 "load_addr=0xa0000000\0" \
224 "kernel_addr_r=0x81000000\0" \
225 "fdt_addr_r=0x90000000\0" \
226 "ramdisk_addr_r=0xa0000000\0" \
227 "kernel_start=0x1000000\0" \
228 "kernelheader_start=0x800000\0" \
229 "kernel_load=0xa0000000\0" \
230 "kernel_size=0x2800000\0" \
231 "kernelheader_size=0x40000\0" \
232 "kernel_addr_sd=0x8000\0" \
233 "kernel_size_sd=0x14000\0" \
234 "kernelhdr_addr_sd=0x4000\0" \
235 "kernelhdr_size_sd=0x10\0" \
236 "console=ttyS0,115200\0" \
237 CONFIG_MTDPARTS_DEFAULT "\0" \
239 "boot_scripts=ls1046ardb_boot.scr\0" \
240 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
241 "scan_dev_for_boot_part=" \
242 "part list ${devtype} ${devnum} devplist; " \
243 "env exists devplist || setenv devplist 1; " \
244 "for distro_bootpart in ${devplist}; do " \
245 "if fstype ${devtype} " \
246 "${devnum}:${distro_bootpart} " \
247 "bootfstype; then " \
248 "run scan_dev_for_boot; " \
252 "load ${devtype} ${devnum}:${distro_bootpart} " \
253 "${scriptaddr} ${prefix}${script}; " \
254 "env exists secureboot && load ${devtype} " \
255 "${devnum}:${distro_bootpart} " \
256 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
257 "env exists secureboot " \
258 "&& esbc_validate ${scripthdraddr};" \
259 "source ${scriptaddr}\0" \
260 "qspi_bootcmd=echo Trying load from qspi..;" \
261 "sf probe && sf read $load_addr " \
262 "$kernel_start $kernel_size; env exists secureboot " \
263 "&& sf read $kernelheader_addr_r $kernelheader_start " \
264 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
265 "bootm $load_addr#$board\0" \
266 "sd_bootcmd=echo Trying load from SD ..;" \
267 "mmcinfo; mmc read $load_addr " \
268 "$kernel_addr_sd $kernel_size_sd && " \
269 "env exists secureboot && mmc read $kernelheader_addr_r " \
270 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
271 " && esbc_validate ${kernelheader_addr_r};" \
272 "bootm $load_addr#$board\0"
276 /* Monitor Command Prompt */
277 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
279 #define CONFIG_SYS_MAXARGS 64 /* max command args */
281 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
283 #include <asm/arch/soc.h>
285 #endif /* __LS1046A_COMMON_H */