1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
6 #ifndef __LS1046A_COMMON_H
7 #define __LS1046A_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
19 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
22 #if defined(CONFIG_SPL_BUILD) && \
23 defined(CONFIG_SD_BOOT) && \
24 !defined(CONFIG_SPL_FSL_LS_PPA)
28 #define CONFIG_REMAKE_ELF
29 #define CONFIG_FSL_LAYERSCAPE
32 #include <asm/arch/config.h>
33 #include <asm/arch/stream_id_lsch2.h>
35 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
38 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #define CONFIG_VERY_BIG_RAM
41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
46 #define CPU_RELEASE_ADDR secondary_boot_func
48 /* Generic Timer Definitions */
49 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
51 /* Size of malloc() pool */
52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
55 #define CONFIG_SYS_NS16550_SERIAL
56 #define CONFIG_SYS_NS16550_REG_SIZE 1
57 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
59 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
63 #define CONFIG_SPL_TEXT_BASE 0x10000000
64 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
65 #define CONFIG_SPL_STACK 0x10020000
66 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
67 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
68 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
69 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
70 CONFIG_SPL_BSS_MAX_SIZE)
71 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
73 #ifdef CONFIG_SECURE_BOOT
74 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
76 * HDR would be appended at end of image and copied to DDR along
77 * with U-Boot image. Here u-boot max. size is 512K. So if binary
78 * size increases then increase this size in case of secure boot as
79 * it uses raw u-boot image instead of fit image.
81 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
83 #define CONFIG_SYS_MONITOR_LEN 0x100000
84 #endif /* ifdef CONFIG_SECURE_BOOT */
88 #ifdef CONFIG_NAND_BOOT
89 #define CONFIG_SPL_PBL_PAD
90 #define CONFIG_SPL_LIBCOMMON_SUPPORT
91 #define CONFIG_SPL_LIBGENERIC_SUPPORT
92 #define CONFIG_SPL_ENV_SUPPORT
93 #define CONFIG_SPL_WATCHDOG_SUPPORT
94 #define CONFIG_SPL_I2C_SUPPORT
95 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
97 #define CONFIG_SPL_NAND_SUPPORT
98 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
99 #define CONFIG_SPL_TEXT_BASE 0x10000000
100 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
101 #define CONFIG_SPL_STACK 0x1001f000
102 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
103 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
106 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
107 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
108 CONFIG_SPL_BSS_MAX_SIZE)
109 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
110 #define CONFIG_SYS_MONITOR_LEN 0xa0000
114 #define CONFIG_SYS_I2C
117 #define CONFIG_PCIE1 /* PCIE controller 1 */
118 #define CONFIG_PCIE2 /* PCIE controller 2 */
119 #define CONFIG_PCIE3 /* PCIE controller 3 */
122 #define CONFIG_PCI_SCAN_SHOW
127 #define CONFIG_SCSI_AHCI_PLAT
129 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
131 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
132 #define CONFIG_SYS_SCSI_MAX_LUN 1
133 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
134 CONFIG_SYS_SCSI_MAX_LUN)
137 /* Command line configuration */
142 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
148 #define CONFIG_SYS_DPAA_FMAN
149 #ifdef CONFIG_SYS_DPAA_FMAN
150 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
153 #ifdef CONFIG_SD_BOOT
155 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
156 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
157 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
159 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
160 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
161 #elif defined(CONFIG_QSPI_BOOT)
162 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
163 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
164 #define CONFIG_ENV_SPI_BUS 0
165 #define CONFIG_ENV_SPI_CS 0
166 #define CONFIG_ENV_SPI_MAX_HZ 1000000
167 #define CONFIG_ENV_SPI_MODE 0x03
168 #elif defined(CONFIG_NAND_BOOT)
169 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
170 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
172 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
173 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
175 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
176 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
179 /* Miscellaneous configurable options */
180 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
182 #define CONFIG_HWCONFIG
183 #define HWCONFIG_BUFFER_SIZE 128
185 #ifndef CONFIG_SPL_BUILD
186 #define BOOT_TARGET_DEVICES(func) \
187 func(SCSI, scsi, 0) \
190 #include <config_distro_bootcmd.h>
194 /* Initial environment variables */
195 #define CONFIG_EXTRA_ENV_SETTINGS \
196 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
197 "ramdisk_addr=0x800000\0" \
198 "ramdisk_size=0x2000000\0" \
199 "fdt_high=0xffffffffffffffff\0" \
200 "initrd_high=0xffffffffffffffff\0" \
201 "fdt_addr=0x64f00000\0" \
202 "kernel_addr=0x65000000\0" \
203 "scriptaddr=0x80000000\0" \
204 "scripthdraddr=0x80080000\0" \
205 "fdtheader_addr_r=0x80100000\0" \
206 "kernelheader_addr_r=0x80200000\0" \
207 "load_addr=0xa0000000\0" \
208 "kernel_addr_r=0x81000000\0" \
209 "fdt_addr_r=0x90000000\0" \
210 "ramdisk_addr_r=0xa0000000\0" \
211 "kernel_start=0x1000000\0" \
212 "kernelheader_start=0x800000\0" \
213 "kernel_load=0xa0000000\0" \
214 "kernel_size=0x2800000\0" \
215 "kernelheader_size=0x40000\0" \
216 "kernel_addr_sd=0x8000\0" \
217 "kernel_size_sd=0x14000\0" \
218 "kernelhdr_addr_sd=0x4000\0" \
219 "kernelhdr_size_sd=0x10\0" \
220 "console=ttyS0,115200\0" \
221 CONFIG_MTDPARTS_DEFAULT "\0" \
223 "boot_scripts=ls1046ardb_boot.scr\0" \
224 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
225 "scan_dev_for_boot_part=" \
226 "part list ${devtype} ${devnum} devplist; " \
227 "env exists devplist || setenv devplist 1; " \
228 "for distro_bootpart in ${devplist}; do " \
229 "if fstype ${devtype} " \
230 "${devnum}:${distro_bootpart} " \
231 "bootfstype; then " \
232 "run scan_dev_for_boot; " \
235 "scan_dev_for_boot=" \
236 "echo Scanning ${devtype} " \
237 "${devnum}:${distro_bootpart}...; " \
238 "for prefix in ${boot_prefixes}; do " \
239 "run scan_dev_for_scripts; " \
243 "load ${devtype} ${devnum}:${distro_bootpart} " \
244 "${scriptaddr} ${prefix}${script}; " \
245 "env exists secureboot && load ${devtype} " \
246 "${devnum}:${distro_bootpart} " \
247 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
248 "&& esbc_validate ${scripthdraddr};" \
249 "source ${scriptaddr}\0" \
250 "qspi_bootcmd=echo Trying load from qspi..;" \
251 "sf probe && sf read $load_addr " \
252 "$kernel_start $kernel_size; env exists secureboot " \
253 "&& sf read $kernelheader_addr_r $kernelheader_start " \
254 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
255 "bootm $load_addr#$board\0" \
256 "sd_bootcmd=echo Trying load from SD ..;" \
257 "mmcinfo; mmc read $load_addr " \
258 "$kernel_addr_sd $kernel_size_sd && " \
259 "env exists secureboot && mmc read $kernelheader_addr_r " \
260 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
261 " && esbc_validate ${kernelheader_addr_r};" \
262 "bootm $load_addr#$board\0"
266 /* Monitor Command Prompt */
267 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
269 #define CONFIG_SYS_MAXARGS 64 /* max command args */
271 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
273 #include <asm/arch/soc.h>
275 #endif /* __LS1046A_COMMON_H */