ARM: zynq: Fix invalid check on NAND_CMD_NONE.
[platform/kernel/u-boot.git] / include / configs / ls1046a_common.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductor
4  * Copyright 2019-2020 NXP
5  */
6
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
9
10 /* SPL build */
11 #ifdef CONFIG_SPL_BUILD
12 #define SPL_NO_QBMAN
13 #define SPL_NO_FMAN
14 #define SPL_NO_ENV
15 #define SPL_NO_MISC
16 #define SPL_NO_QSPI
17 #define SPL_NO_USB
18 #define SPL_NO_SATA
19 #undef CONFIG_DM_I2C
20 #endif
21 #if defined(CONFIG_SPL_BUILD) && \
22         (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
23 #define SPL_NO_MMC
24 #endif
25 #if defined(CONFIG_SPL_BUILD)           && \
26         !defined(CONFIG_SPL_FSL_LS_PPA)
27 #define SPL_NO_IFC
28 #endif
29
30 #define CONFIG_REMAKE_ELF
31 #define CONFIG_GICV2
32
33 #include <asm/arch/config.h>
34 #include <asm/arch/stream_id_lsch2.h>
35
36 /* Link Definitions */
37 #ifdef CONFIG_TFABOOT
38 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
39 #else
40 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
41 #endif
42
43 #define CONFIG_SKIP_LOWLEVEL_INIT
44
45 #define CONFIG_VERY_BIG_RAM
46 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
47 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
48 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
50
51 #define CPU_RELEASE_ADDR               secondary_boot_func
52
53 /* Generic Timer Definitions */
54 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
55
56 /* Size of malloc() pool */
57 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
58
59 /* Serial Port */
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE     1
62 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
63
64 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
65
66 /* SD boot SPL */
67 #ifdef CONFIG_SD_BOOT
68 #define CONFIG_SPL_MAX_SIZE             0x1f000         /* 124 KiB */
69 #define CONFIG_SPL_STACK                0x10020000
70 #define CONFIG_SPL_PAD_TO               0x21000         /* 132 KiB */
71 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
72 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
73 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
74                                         CONFIG_SPL_BSS_MAX_SIZE)
75 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
76
77 #ifdef CONFIG_NXP_ESBC
78 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
79 /*
80  * HDR would be appended at end of image and copied to DDR along
81  * with U-Boot image. Here u-boot max. size is 512K. So if binary
82  * size increases then increase this size in case of secure boot as
83  * it uses raw u-boot image instead of fit image.
84  */
85 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
86 #else
87 #define CONFIG_SYS_MONITOR_LEN          0x100000
88 #endif /* ifdef CONFIG_NXP_ESBC */
89 #endif
90
91 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
92 #define CONFIG_SPL_TARGET               "spl/u-boot-spl.pbl"
93 #define CONFIG_SPL_MAX_SIZE             0x1f000
94 #define CONFIG_SPL_STACK                0x10020000
95 #define CONFIG_SPL_PAD_TO               0x20000
96 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
97 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
98 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
99                                         CONFIG_SPL_BSS_MAX_SIZE)
100 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
101 #define CONFIG_SYS_MONITOR_LEN          0x100000
102 #endif
103
104 /* NAND SPL */
105 #ifdef CONFIG_NAND_BOOT
106 #define CONFIG_SPL_PBL_PAD
107 #define CONFIG_SPL_LIBCOMMON_SUPPORT
108 #define CONFIG_SPL_LIBGENERIC_SUPPORT
109 #define CONFIG_SPL_ENV_SUPPORT
110 #define CONFIG_SPL_WATCHDOG_SUPPORT
111 #define CONFIG_SPL_I2C_SUPPORT
112 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
113
114 #define CONFIG_SPL_NAND_SUPPORT
115 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
116 #define CONFIG_SPL_MAX_SIZE             0x17000         /* 90 KiB */
117 #define CONFIG_SPL_STACK                0x1001f000
118 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
120
121 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
122 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
123 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
124                                         CONFIG_SPL_BSS_MAX_SIZE)
125 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
126 #define CONFIG_SYS_MONITOR_LEN          0xa0000
127 #endif
128
129 /* I2C */
130 #ifndef CONFIG_DM_I2C
131 #define CONFIG_SYS_I2C
132 #define CONFIG_SYS_I2C_MXC
133 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
134 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
135 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
136 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
137 #else
138 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
139 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
140 #endif
141
142 /* PCIe */
143 #define CONFIG_PCIE1            /* PCIE controller 1 */
144 #define CONFIG_PCIE2            /* PCIE controller 2 */
145 #define CONFIG_PCIE3            /* PCIE controller 3 */
146
147 #ifdef CONFIG_PCI
148 #define CONFIG_PCI_SCAN_SHOW
149 #endif
150
151 /* SATA */
152 #ifndef SPL_NO_SATA
153 #define CONFIG_SCSI_AHCI_PLAT
154
155 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
156
157 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
158 #define CONFIG_SYS_SCSI_MAX_LUN                 1
159 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
160                                                 CONFIG_SYS_SCSI_MAX_LUN)
161 #endif
162
163 /* Command line configuration */
164
165 /* MMC */
166 #ifndef SPL_NO_MMC
167 #ifdef CONFIG_MMC
168 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
169 #endif
170 #endif
171
172 /* FMan ucode */
173 #ifndef SPL_NO_FMAN
174 #define CONFIG_SYS_DPAA_FMAN
175 #ifdef CONFIG_SYS_DPAA_FMAN
176 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
177 #endif
178
179 #ifdef CONFIG_TFABOOT
180 #define CONFIG_SYS_FMAN_FW_ADDR         0x900000
181 #else
182 #ifdef CONFIG_SD_BOOT
183 /*
184  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
185  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
186  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
187  */
188 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x4800)
189 #elif defined(CONFIG_QSPI_BOOT)
190 #define CONFIG_SYS_FMAN_FW_ADDR         0x40900000
191 #elif defined(CONFIG_NAND_BOOT)
192 #define CONFIG_SYS_FMAN_FW_ADDR         (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
193 #else
194 #define CONFIG_SYS_FMAN_FW_ADDR         0x60900000
195 #endif
196 #endif
197 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
198 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
199 #endif
200
201 /* Miscellaneous configurable options */
202 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
203
204 #define CONFIG_HWCONFIG
205 #define HWCONFIG_BUFFER_SIZE            128
206
207 #ifndef CONFIG_SPL_BUILD
208 #define BOOT_TARGET_DEVICES(func) \
209         func(SCSI, scsi, 0) \
210         func(MMC, mmc, 0) \
211         func(USB, usb, 0) \
212         func(DHCP, dhcp, na)
213 #include <config_distro_bootcmd.h>
214 #endif
215
216 #if defined(CONFIG_TARGET_LS1046AFRWY)
217 #define LS1046A_BOOT_SRC_AND_HDR\
218         "boot_scripts=ls1046afrwy_boot.scr\0"   \
219         "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
220 #else
221 #define LS1046A_BOOT_SRC_AND_HDR\
222         "boot_scripts=ls1046ardb_boot.scr\0"    \
223         "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
224 #endif
225 #ifndef SPL_NO_MISC
226 /* Initial environment variables */
227 #define CONFIG_EXTRA_ENV_SETTINGS               \
228         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
229         "ramdisk_addr=0x800000\0"               \
230         "ramdisk_size=0x2000000\0"              \
231         "bootm_size=0x10000000\0"               \
232         "fdt_addr=0x64f00000\0"                 \
233         "kernel_addr=0x65000000\0"              \
234         "scriptaddr=0x80000000\0"               \
235         "scripthdraddr=0x80080000\0"            \
236         "fdtheader_addr_r=0x80100000\0"         \
237         "kernelheader_addr_r=0x80200000\0"      \
238         "load_addr=0xa0000000\0"            \
239         "kernel_addr_r=0x81000000\0"            \
240         "fdt_addr_r=0x90000000\0"               \
241         "ramdisk_addr_r=0xa0000000\0"           \
242         "kernel_start=0x1000000\0"              \
243         "kernelheader_start=0x600000\0"         \
244         "kernel_load=0xa0000000\0"              \
245         "kernel_size=0x2800000\0"               \
246         "kernelheader_size=0x40000\0"           \
247         "kernel_addr_sd=0x8000\0"               \
248         "kernel_size_sd=0x14000\0"              \
249         "kernelhdr_addr_sd=0x3000\0"            \
250         "kernelhdr_size_sd=0x10\0"              \
251         "console=ttyS0,115200\0"                \
252          CONFIG_MTDPARTS_DEFAULT "\0"           \
253         BOOTENV                                 \
254         LS1046A_BOOT_SRC_AND_HDR                \
255         "scan_dev_for_boot_part="               \
256                 "part list ${devtype} ${devnum} devplist; "   \
257                 "env exists devplist || setenv devplist 1; "  \
258                 "for distro_bootpart in ${devplist}; do "     \
259                   "if fstype ${devtype} "                  \
260                         "${devnum}:${distro_bootpart} "      \
261                         "bootfstype; then "                  \
262                         "run scan_dev_for_boot; "            \
263                   "fi; "                                   \
264                 "done\0"                                   \
265         "boot_a_script="                                  \
266                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
267                         "${scriptaddr} ${prefix}${script}; "    \
268                 "env exists secureboot && load ${devtype} "     \
269                         "${devnum}:${distro_bootpart} "         \
270                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
271                         "env exists secureboot "        \
272                         "&& esbc_validate ${scripthdraddr};"    \
273                 "source ${scriptaddr}\0"          \
274         "qspi_bootcmd=echo Trying load from qspi..;"      \
275                 "sf probe && sf read $load_addr "         \
276                 "$kernel_start $kernel_size; env exists secureboot "    \
277                 "&& sf read $kernelheader_addr_r $kernelheader_start "  \
278                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
279                 "bootm $load_addr#$board\0"             \
280         "sd_bootcmd=echo Trying load from SD ..;"       \
281                 "mmcinfo; mmc read $load_addr "         \
282                 "$kernel_addr_sd $kernel_size_sd && "   \
283                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
284                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
285                 " && esbc_validate ${kernelheader_addr_r};"     \
286                 "bootm $load_addr#$board\0"
287
288 #endif
289
290 /* Monitor Command Prompt */
291 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
292
293 #define CONFIG_SYS_MAXARGS              64      /* max command args */
294
295 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
296
297 #include <asm/arch/soc.h>
298
299 #endif /* __LS1046A_COMMON_H */