1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
4 * Copyright 2019-2020 NXP
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
21 #if defined(CONFIG_SPL_BUILD) && \
22 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
25 #if defined(CONFIG_SPL_BUILD) && \
26 !defined(CONFIG_SPL_FSL_LS_PPA)
30 #define CONFIG_REMAKE_ELF
33 #include <asm/arch/config.h>
34 #include <asm/arch/stream_id_lsch2.h>
36 /* Link Definitions */
38 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
43 #define CONFIG_SKIP_LOWLEVEL_INIT
45 #define CONFIG_VERY_BIG_RAM
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
47 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
51 #define CPU_RELEASE_ADDR secondary_boot_func
53 /* Generic Timer Definitions */
54 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
56 /* Size of malloc() pool */
57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE 1
62 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
68 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
69 #define CONFIG_SPL_STACK 0x10020000
70 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
71 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
72 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
73 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
74 CONFIG_SPL_BSS_MAX_SIZE)
75 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
77 #ifdef CONFIG_NXP_ESBC
78 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
80 * HDR would be appended at end of image and copied to DDR along
81 * with U-Boot image. Here u-boot max. size is 512K. So if binary
82 * size increases then increase this size in case of secure boot as
83 * it uses raw u-boot image instead of fit image.
85 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
87 #define CONFIG_SYS_MONITOR_LEN 0x100000
88 #endif /* ifdef CONFIG_NXP_ESBC */
91 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
92 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
93 #define CONFIG_SPL_MAX_SIZE 0x1f000
94 #define CONFIG_SPL_STACK 0x10020000
95 #define CONFIG_SPL_PAD_TO 0x20000
96 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
97 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
98 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
99 CONFIG_SPL_BSS_MAX_SIZE)
100 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
101 #define CONFIG_SYS_MONITOR_LEN 0x100000
105 #ifdef CONFIG_NAND_BOOT
106 #define CONFIG_SPL_PBL_PAD
107 #define CONFIG_SPL_LIBCOMMON_SUPPORT
108 #define CONFIG_SPL_LIBGENERIC_SUPPORT
109 #define CONFIG_SPL_ENV_SUPPORT
110 #define CONFIG_SPL_WATCHDOG_SUPPORT
111 #define CONFIG_SPL_I2C_SUPPORT
112 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
114 #define CONFIG_SPL_NAND_SUPPORT
115 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
116 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
117 #define CONFIG_SPL_STACK 0x1001f000
118 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
121 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
124 CONFIG_SPL_BSS_MAX_SIZE)
125 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
126 #define CONFIG_SYS_MONITOR_LEN 0xa0000
130 #ifndef CONFIG_DM_I2C
131 #define CONFIG_SYS_I2C
132 #define CONFIG_SYS_I2C_MXC
133 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
134 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
135 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
136 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
138 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
139 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
143 #define CONFIG_PCIE1 /* PCIE controller 1 */
144 #define CONFIG_PCIE2 /* PCIE controller 2 */
145 #define CONFIG_PCIE3 /* PCIE controller 3 */
148 #define CONFIG_PCI_SCAN_SHOW
153 #define CONFIG_SCSI_AHCI_PLAT
155 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
157 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
158 #define CONFIG_SYS_SCSI_MAX_LUN 1
159 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
160 CONFIG_SYS_SCSI_MAX_LUN)
166 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
172 #define CONFIG_SYS_DPAA_FMAN
173 #ifdef CONFIG_SYS_DPAA_FMAN
174 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
177 #ifdef CONFIG_TFABOOT
178 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
180 #ifdef CONFIG_SD_BOOT
182 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
183 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
184 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
186 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
187 #elif defined(CONFIG_QSPI_BOOT)
188 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
189 #elif defined(CONFIG_NAND_BOOT)
190 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
192 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
195 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
196 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
199 /* Miscellaneous configurable options */
200 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
202 #define CONFIG_HWCONFIG
203 #define HWCONFIG_BUFFER_SIZE 128
205 #ifndef CONFIG_SPL_BUILD
206 #define BOOT_TARGET_DEVICES(func) \
207 func(SCSI, scsi, 0) \
211 #include <config_distro_bootcmd.h>
214 #if defined(CONFIG_TARGET_LS1046AFRWY)
215 #define LS1046A_BOOT_SRC_AND_HDR\
216 "boot_scripts=ls1046afrwy_boot.scr\0" \
217 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
218 #elif defined(CONFIG_TARGET_LS1046AQDS)
219 #define LS1046A_BOOT_SRC_AND_HDR\
220 "boot_scripts=ls1046aqds_boot.scr\0" \
221 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
223 #define LS1046A_BOOT_SRC_AND_HDR\
224 "boot_scripts=ls1046ardb_boot.scr\0" \
225 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
228 /* Initial environment variables */
229 #define CONFIG_EXTRA_ENV_SETTINGS \
230 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
231 "ramdisk_addr=0x800000\0" \
232 "ramdisk_size=0x2000000\0" \
233 "bootm_size=0x10000000\0" \
234 "fdt_addr=0x64f00000\0" \
235 "kernel_addr=0x61000000\0" \
236 "scriptaddr=0x80000000\0" \
237 "scripthdraddr=0x80080000\0" \
238 "fdtheader_addr_r=0x80100000\0" \
239 "kernelheader_addr_r=0x80200000\0" \
240 "load_addr=0xa0000000\0" \
241 "kernel_addr_r=0x81000000\0" \
242 "fdt_addr_r=0x90000000\0" \
243 "ramdisk_addr_r=0xa0000000\0" \
244 "kernel_start=0x1000000\0" \
245 "kernelheader_start=0x600000\0" \
246 "kernel_load=0xa0000000\0" \
247 "kernel_size=0x2800000\0" \
248 "kernelheader_size=0x40000\0" \
249 "kernel_addr_sd=0x8000\0" \
250 "kernel_size_sd=0x14000\0" \
251 "kernelhdr_addr_sd=0x3000\0" \
252 "kernelhdr_size_sd=0x10\0" \
253 "console=ttyS0,115200\0" \
254 CONFIG_MTDPARTS_DEFAULT "\0" \
256 LS1046A_BOOT_SRC_AND_HDR \
257 "scan_dev_for_boot_part=" \
258 "part list ${devtype} ${devnum} devplist; " \
259 "env exists devplist || setenv devplist 1; " \
260 "for distro_bootpart in ${devplist}; do " \
261 "if fstype ${devtype} " \
262 "${devnum}:${distro_bootpart} " \
263 "bootfstype; then " \
264 "run scan_dev_for_boot; " \
268 "load ${devtype} ${devnum}:${distro_bootpart} " \
269 "${scriptaddr} ${prefix}${script}; " \
270 "env exists secureboot && load ${devtype} " \
271 "${devnum}:${distro_bootpart} " \
272 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
273 "env exists secureboot " \
274 "&& esbc_validate ${scripthdraddr};" \
275 "source ${scriptaddr}\0" \
276 "qspi_bootcmd=echo Trying load from qspi..;" \
277 "sf probe && sf read $load_addr " \
278 "$kernel_start $kernel_size; env exists secureboot " \
279 "&& sf read $kernelheader_addr_r $kernelheader_start " \
280 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
281 "bootm $load_addr#$board\0" \
282 "nand_bootcmd=echo Trying load from nand..;" \
283 "nand info; nand read $load_addr " \
284 "$kernel_start $kernel_size; env exists secureboot " \
285 "&& nand read $kernelheader_addr_r $kernelheader_start " \
286 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
287 "bootm $load_addr#$board\0" \
288 "nor_bootcmd=echo Trying load from nor..;" \
289 "cp.b $kernel_addr $load_addr " \
290 "$kernel_size; env exists secureboot " \
291 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
292 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
293 "bootm $load_addr#$board\0" \
294 "sd_bootcmd=echo Trying load from SD ..;" \
295 "mmcinfo; mmc read $load_addr " \
296 "$kernel_addr_sd $kernel_size_sd && " \
297 "env exists secureboot && mmc read $kernelheader_addr_r " \
298 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
299 " && esbc_validate ${kernelheader_addr_r};" \
300 "bootm $load_addr#$board\0"
304 /* Monitor Command Prompt */
305 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
307 #define CONFIG_SYS_MAXARGS 64 /* max command args */
309 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
311 #include <asm/arch/soc.h>
313 #endif /* __LS1046A_COMMON_H */