1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
20 #if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
24 #if defined(CONFIG_SPL_BUILD) && \
25 !defined(CONFIG_SPL_FSL_LS_PPA)
29 #include <asm/arch/config.h>
30 #include <asm/arch/stream_id_lsch2.h>
32 /* Link Definitions */
34 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 #define CONFIG_VERY_BIG_RAM
40 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
41 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
42 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
43 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
45 #define CPU_RELEASE_ADDR secondary_boot_addr
47 /* Generic Timer Definitions */
48 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE 1
53 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
57 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
58 #define CONFIG_SPL_STACK 0x10020000
59 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
60 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
61 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
62 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
63 CONFIG_SPL_BSS_MAX_SIZE)
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
66 #ifdef CONFIG_NXP_ESBC
67 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
69 * HDR would be appended at end of image and copied to DDR along
70 * with U-Boot image. Here u-boot max. size is 512K. So if binary
71 * size increases then increase this size in case of secure boot as
72 * it uses raw u-boot image instead of fit image.
74 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
76 #define CONFIG_SYS_MONITOR_LEN 0x100000
77 #endif /* ifdef CONFIG_NXP_ESBC */
80 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
81 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
82 #define CONFIG_SPL_MAX_SIZE 0x1f000
83 #define CONFIG_SPL_STACK 0x10020000
84 #define CONFIG_SPL_PAD_TO 0x20000
85 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
87 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
88 CONFIG_SPL_BSS_MAX_SIZE)
89 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
90 #define CONFIG_SYS_MONITOR_LEN 0x100000
94 #ifdef CONFIG_NAND_BOOT
95 #define CONFIG_SPL_PBL_PAD
97 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
98 #define CONFIG_SPL_STACK 0x1001f000
99 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
100 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
102 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
103 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
104 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
105 CONFIG_SPL_BSS_MAX_SIZE)
106 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
107 #define CONFIG_SYS_MONITOR_LEN 0xa0000
115 #define CONFIG_PCIE1 /* PCIE controller 1 */
116 #define CONFIG_PCIE2 /* PCIE controller 2 */
117 #define CONFIG_PCIE3 /* PCIE controller 3 */
120 #define CONFIG_PCI_SCAN_SHOW
125 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
130 #define CONFIG_SYS_DPAA_FMAN
131 #ifdef CONFIG_SYS_DPAA_FMAN
132 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
134 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
137 /* Miscellaneous configurable options */
139 #define CONFIG_HWCONFIG
140 #define HWCONFIG_BUFFER_SIZE 128
142 #ifndef CONFIG_SPL_BUILD
143 #define BOOT_TARGET_DEVICES(func) \
144 func(SCSI, scsi, 0) \
148 #include <config_distro_bootcmd.h>
151 #if defined(CONFIG_TARGET_LS1046AFRWY)
152 #define LS1046A_BOOT_SRC_AND_HDR\
153 "boot_scripts=ls1046afrwy_boot.scr\0" \
154 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
155 #elif defined(CONFIG_TARGET_LS1046AQDS)
156 #define LS1046A_BOOT_SRC_AND_HDR\
157 "boot_scripts=ls1046aqds_boot.scr\0" \
158 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
160 #define LS1046A_BOOT_SRC_AND_HDR\
161 "boot_scripts=ls1046ardb_boot.scr\0" \
162 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
165 /* Initial environment variables */
166 #define CONFIG_EXTRA_ENV_SETTINGS \
167 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
168 "ramdisk_addr=0x800000\0" \
169 "ramdisk_size=0x2000000\0" \
170 "bootm_size=0x10000000\0" \
171 "fdt_addr=0x64f00000\0" \
172 "kernel_addr=0x61000000\0" \
173 "scriptaddr=0x80000000\0" \
174 "scripthdraddr=0x80080000\0" \
175 "fdtheader_addr_r=0x80100000\0" \
176 "kernelheader_addr_r=0x80200000\0" \
177 "load_addr=0xa0000000\0" \
178 "kernel_addr_r=0x81000000\0" \
179 "fdt_addr_r=0x90000000\0" \
180 "ramdisk_addr_r=0xa0000000\0" \
181 "kernel_start=0x1000000\0" \
182 "kernelheader_start=0x600000\0" \
183 "kernel_load=0xa0000000\0" \
184 "kernel_size=0x2800000\0" \
185 "kernelheader_size=0x40000\0" \
186 "kernel_addr_sd=0x8000\0" \
187 "kernel_size_sd=0x14000\0" \
188 "kernelhdr_addr_sd=0x3000\0" \
189 "kernelhdr_size_sd=0x10\0" \
190 "console=ttyS0,115200\0" \
191 CONFIG_MTDPARTS_DEFAULT "\0" \
193 LS1046A_BOOT_SRC_AND_HDR \
194 "scan_dev_for_boot_part=" \
195 "part list ${devtype} ${devnum} devplist; " \
196 "env exists devplist || setenv devplist 1; " \
197 "for distro_bootpart in ${devplist}; do " \
198 "if fstype ${devtype} " \
199 "${devnum}:${distro_bootpart} " \
200 "bootfstype; then " \
201 "run scan_dev_for_boot; " \
205 "load ${devtype} ${devnum}:${distro_bootpart} " \
206 "${scriptaddr} ${prefix}${script}; " \
207 "env exists secureboot && load ${devtype} " \
208 "${devnum}:${distro_bootpart} " \
209 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
210 "env exists secureboot " \
211 "&& esbc_validate ${scripthdraddr};" \
212 "source ${scriptaddr}\0" \
213 "qspi_bootcmd=echo Trying load from qspi..;" \
214 "sf probe && sf read $load_addr " \
215 "$kernel_start $kernel_size; env exists secureboot " \
216 "&& sf read $kernelheader_addr_r $kernelheader_start " \
217 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
218 "bootm $load_addr#$board\0" \
219 "nand_bootcmd=echo Trying load from nand..;" \
220 "nand info; nand read $load_addr " \
221 "$kernel_start $kernel_size; env exists secureboot " \
222 "&& nand read $kernelheader_addr_r $kernelheader_start " \
223 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
224 "bootm $load_addr#$board\0" \
225 "nor_bootcmd=echo Trying load from nor..;" \
226 "cp.b $kernel_addr $load_addr " \
227 "$kernel_size; env exists secureboot " \
228 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
229 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
230 "bootm $load_addr#$board\0" \
231 "sd_bootcmd=echo Trying load from SD ..;" \
232 "mmcinfo; mmc read $load_addr " \
233 "$kernel_addr_sd $kernel_size_sd && " \
234 "env exists secureboot && mmc read $kernelheader_addr_r " \
235 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
236 " && esbc_validate ${kernelheader_addr_r};" \
237 "bootm $load_addr#$board\0"
241 /* Monitor Command Prompt */
242 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
244 #define CONFIG_SYS_MAXARGS 64 /* max command args */
246 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
248 #include <asm/arch/soc.h>
250 #endif /* __LS1046A_COMMON_H */