include/configs/ls1046a_common.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1046A_COMMON_H
   8 #define __LS1046A_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_MP
  13 #define CONFIG_GICV2
  14
  15 #include <asm/arch/config.h>
  16
  17 /* Link Definitions */
  18 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  19
  20 #define CONFIG_SUPPORT_RAW_INITRD
  21
  22 #define CONFIG_SKIP_LOWLEVEL_INIT
  23
  24 #define CONFIG_VERY_BIG_RAM
  25 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  26 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  27 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  28 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  29
  30 #define CPU_RELEASE_ADDR               secondary_boot_func
  31
  32 /* Generic Timer Definitions */
  33 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  34
  35 /* Size of malloc() pool */
  36 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  37
  38 /* Serial Port */
  39 #define CONFIG_CONS_INDEX               1
  40 #define CONFIG_SYS_NS16550_SERIAL
  41 #define CONFIG_SYS_NS16550_REG_SIZE     1
  42 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  43
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  45
  46 /* SD boot SPL */
  47 #ifdef CONFIG_SD_BOOT
  48 #define CONFIG_SPL_FRAMEWORK
  49 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  50 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  51 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  52 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  53 #define CONFIG_SPL_ENV_SUPPORT
  54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  55 #define CONFIG_SPL_WATCHDOG_SUPPORT
  56 #define CONFIG_SPL_I2C_SUPPORT
  57 #define CONFIG_SPL_SERIAL_SUPPORT
  58 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  59
  60 #define CONFIG_SPL_MMC_SUPPORT
  61 #define CONFIG_SPL_TEXT_BASE            0x10000000
  62 #define CONFIG_SPL_MAX_SIZE             0x1f000         /* 124 KiB */
  63 #define CONFIG_SPL_STACK                0x10020000
  64 #define CONFIG_SPL_PAD_TO               0x21000         /* 132 KiB */
  65 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  66 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  67 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  68                                         CONFIG_SPL_BSS_MAX_SIZE)
  69 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  70 #define CONFIG_SYS_MONITOR_LEN          0xa0000
  71 #endif
  72
  73 /* NAND SPL */
  74 #ifdef CONFIG_NAND_BOOT
  75 #define CONFIG_SPL_PBL_PAD
  76 #define CONFIG_SPL_FRAMEWORK
  77 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  78 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  79 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  80 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  81 #define CONFIG_SPL_ENV_SUPPORT
  82 #define CONFIG_SPL_WATCHDOG_SUPPORT
  83 #define CONFIG_SPL_I2C_SUPPORT
  84 #define CONFIG_SPL_SERIAL_SUPPORT
  85 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  86
  87 #define CONFIG_SPL_NAND_SUPPORT
  88 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  89 #define CONFIG_SPL_TEXT_BASE            0x10000000
  90 #define CONFIG_SPL_MAX_SIZE             0x1d000         /* 116 KiB */
  91 #define CONFIG_SPL_STACK                0x1001f000
  92 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  93 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  94
  95 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  96 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  97 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  98                                         CONFIG_SPL_BSS_MAX_SIZE)
  99 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 100 #define CONFIG_SYS_MONITOR_LEN          0xa0000
 101 #endif
 102
 103 /* I2C */
 104 #define CONFIG_SYS_I2C
 105 #define CONFIG_SYS_I2C_MXC
 106 #define CONFIG_SYS_I2C_MXC_I2C1
 107 #define CONFIG_SYS_I2C_MXC_I2C2
 108 #define CONFIG_SYS_I2C_MXC_I2C3
 109 #define CONFIG_SYS_I2C_MXC_I2C4
 110
 111 /* Command line configuration */
 112 #define CONFIG_CMD_ENV
 113
 114 /* MMC */
 115 #ifdef CONFIG_MMC
 116 #define CONFIG_FSL_ESDHC
 117 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 118 #endif
 119
 120 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 121
 122 /* FMan ucode */
 123 #define CONFIG_SYS_DPAA_FMAN
 124 #ifdef CONFIG_SYS_DPAA_FMAN
 125 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 126
 127 #ifdef CONFIG_SD_BOOT
 128 /*
 129  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 130  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 131  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 132  */
 133 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 134 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 135 #elif defined(CONFIG_QSPI_BOOT)
 136 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 137 #define CONFIG_SYS_FMAN_FW_ADDR         0x40300000
 138 #define CONFIG_ENV_SPI_BUS              0
 139 #define CONFIG_ENV_SPI_CS               0
 140 #define CONFIG_ENV_SPI_MAX_HZ           1000000
 141 #define CONFIG_ENV_SPI_MODE             0x03
 142 #elif defined(CONFIG_NAND_BOOT)
 143 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 144 #define CONFIG_SYS_FMAN_FW_ADDR         (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 145 #else
 146 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 147 #define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 148 #endif
 149 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 150 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 151 #endif
 152
 153 /* Miscellaneous configurable options */
 154 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 155
 156 #define CONFIG_HWCONFIG
 157 #define HWCONFIG_BUFFER_SIZE            128
 158
 159 /* Initial environment variables */
 160 #define CONFIG_EXTRA_ENV_SETTINGS               \
 161         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 162         "loadaddr=0x80100000\0"                 \
 163         "ramdisk_addr=0x800000\0"               \
 164         "ramdisk_size=0x2000000\0"              \
 165         "fdt_high=0xffffffffffffffff\0"         \
 166         "initrd_high=0xffffffffffffffff\0"      \
 167         "kernel_start=0x1000000\0"              \
 168         "kernel_load=0xa0000000\0"              \
 169         "kernel_size=0x2800000\0"               \
 170         "console=ttyS0,115200\0"                \
 171                 MTDPARTS_DEFAULT "\0"
 172
 173 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 174                                         "earlycon=uart8250,mmio,0x21c0500 " \
 175                                         MTDPARTS_DEFAULT
 176 /* Monitor Command Prompt */
 177 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 178 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 179                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 180 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 181 #define CONFIG_SYS_LONGHELP
 182 #define CONFIG_CMDLINE_EDITING          1
 183 #define CONFIG_AUTO_COMPLETE
 184 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 185
 186 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 187
 188 /* Hash command with SHA acceleration supported in hardware */
 189 #ifdef CONFIG_FSL_CAAM
 190 #define CONFIG_CMD_HASH
 191 #define CONFIG_SHA_HW_ACCEL
 192 #endif
 193
 194 #endif /* __LS1046A_COMMON_H */