1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor
6 #ifndef __LS1043ARDB_H__
7 #define __LS1043ARDB_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_SYS_CLK_FREQ 100000000
13 #define CONFIG_LAYERSCAPE_NS_ACCESS
15 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
16 /* Physical Memory Map */
17 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
19 #define CONFIG_SYS_SPD_BUS_NUM 0
22 #define CONFIG_SYS_DDR_RAW_TIMING
23 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
24 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
27 #ifdef CONFIG_RAMBOOT_PBL
28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
31 #ifdef CONFIG_NAND_BOOT
32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
37 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
38 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
39 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
40 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
44 * NOR Flash Definitions
46 #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
47 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
48 #define CONFIG_SYS_NOR_CSPR \
49 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
54 /* NOR Flash Timing Params */
55 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
57 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
58 FTIM0_NOR_TEADC(0x1) | \
59 FTIM0_NOR_TAVDS(0x0) | \
61 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
62 FTIM1_NOR_TRAD_NOR(0xb) | \
63 FTIM1_NOR_TSEQRAD_NOR(0x9))
64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
65 FTIM2_NOR_TCH(0x4) | \
66 FTIM2_NOR_TWPH(0x8) | \
68 #define CONFIG_SYS_NOR_FTIM3 0
69 #define CONFIG_SYS_IFC_CCR 0x01000000
71 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
72 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
73 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
74 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
76 #define CONFIG_SYS_FLASH_EMPTY_INFO
77 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
79 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
80 #define CONFIG_SYS_WRITE_SWAPPED_DATA
83 * NAND Flash Definitions
86 #define CONFIG_NAND_FSL_IFC
89 #define CONFIG_SYS_NAND_BASE 0x7e800000
90 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
92 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
93 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
97 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
98 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
99 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
100 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
101 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
102 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
103 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
104 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
106 #define CONFIG_SYS_NAND_ONFI_DETECTION
108 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
109 FTIM0_NAND_TWP(0x18) | \
110 FTIM0_NAND_TWCHT(0x7) | \
112 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
113 FTIM1_NAND_TWBE(0x39) | \
114 FTIM1_NAND_TRR(0xe) | \
115 FTIM1_NAND_TRP(0x18))
116 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
117 FTIM2_NAND_TREH(0xa) | \
118 FTIM2_NAND_TWHRE(0x1e))
119 #define CONFIG_SYS_NAND_FTIM3 0x0
121 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
122 #define CONFIG_SYS_MAX_NAND_DEVICE 1
123 #define CONFIG_MTD_NAND_VERIFY_WRITE
125 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
127 #ifdef CONFIG_NAND_BOOT
128 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
130 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
136 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
137 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
139 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
140 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
144 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
145 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
146 CSOR_NOR_NOR_MODE_AVD_NOR | \
149 /* CPLD Timing parameters for IFC GPCM */
150 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
151 FTIM0_GPCM_TEADC(0xf) | \
152 FTIM0_GPCM_TEAHC(0xf))
153 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
154 FTIM1_GPCM_TRAD(0x3f))
155 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
156 FTIM2_GPCM_TCH(0xf) | \
157 FTIM2_GPCM_TWP(0xff))
158 #define CONFIG_SYS_CPLD_FTIM3 0x0
160 /* IFC Timing Params */
161 #ifdef CONFIG_TFABOOT
162 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
163 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
164 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
165 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
166 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
167 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
168 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
169 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
171 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
172 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
173 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
174 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
175 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
176 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
177 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
178 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
180 #ifdef CONFIG_NAND_BOOT
181 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
182 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
183 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
184 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
185 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
186 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
187 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
188 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
190 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
191 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
192 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
193 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
194 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
195 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
196 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
197 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
199 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
200 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
201 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
202 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
203 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
204 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
205 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
206 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
208 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
209 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
210 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
211 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
212 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
213 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
214 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
215 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
219 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
220 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
221 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
222 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
223 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
224 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
225 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
226 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
229 #ifndef SPL_NO_EEPROM
230 #define CONFIG_SYS_I2C_EEPROM_NXID
231 #define CONFIG_SYS_EEPROM_BUS_NUM 0
240 #define AQR105_IRQ_MASK 0x40000000
242 #ifdef CONFIG_SYS_DPAA_FMAN
243 #define RGMII_PHY1_ADDR 0x1
244 #define RGMII_PHY2_ADDR 0x2
246 #define QSGMII_PORT1_PHY_ADDR 0x4
247 #define QSGMII_PORT2_PHY_ADDR 0x5
248 #define QSGMII_PORT3_PHY_ADDR 0x6
249 #define QSGMII_PORT4_PHY_ADDR 0x7
251 #define FM1_10GEC1_PHY_ADDR 0x1
253 #define CONFIG_ETHPRIME "FM1@DTSEC3"
259 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
260 #define CONFIG_SYS_SCSI_MAX_LUN 2
261 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
262 CONFIG_SYS_SCSI_MAX_LUN)
263 #define SCSI_VEND_ID 0x1b4b
264 #define SCSI_DEV_ID 0x9170
265 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
268 #include <asm/fsl_secure_boot.h>
270 #endif /* __LS1043ARDB_H__ */