include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12
  13 #define CONFIG_LAYERSCAPE_NS_ACCESS
  14
  15 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  16 /* Physical Memory Map */
  17 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  18
  19 #define CONFIG_SYS_SPD_BUS_NUM          0
  20
  21 #ifndef CONFIG_SPL
  22 #define CONFIG_SYS_DDR_RAW_TIMING
  23 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  24 #endif
  25
  26 #ifdef CONFIG_RAMBOOT_PBL
  27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  28 #endif
  29
  30 #ifdef CONFIG_NAND_BOOT
  31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  32 #endif
  33
  34 #ifdef CONFIG_SD_BOOT
  35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  36 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  37 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  38 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  39 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  40 #endif
  41
  42 /*
  43  * NOR Flash Definitions
  44  */
  45 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  46 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  47 #define CONFIG_SYS_NOR_CSPR                                     \
  48         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  49         CSPR_PORT_SIZE_16                                       | \
  50         CSPR_MSEL_NOR                                           | \
  51         CSPR_V)
  52
  53 /* NOR Flash Timing Params */
  54 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  55                                         CSOR_NOR_TRHZ_80)
  56 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  57                                         FTIM0_NOR_TEADC(0x1) | \
  58                                         FTIM0_NOR_TAVDS(0x0) | \
  59                                         FTIM0_NOR_TEAHC(0xc))
  60 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  61                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  62                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  63 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  64                                         FTIM2_NOR_TCH(0x4) | \
  65                                         FTIM2_NOR_TWPH(0x8) | \
  66                                         FTIM2_NOR_TWP(0x10))
  67 #define CONFIG_SYS_NOR_FTIM3            0
  68 #define CONFIG_SYS_IFC_CCR              0x01000000
  69
  70 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  71 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  72 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  73 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  74
  75 #define CONFIG_SYS_FLASH_EMPTY_INFO
  76 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  77
  78 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  79 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  80
  81 /*
  82  * NAND Flash Definitions
  83  */
  84 #ifndef SPL_NO_IFC
  85 #define CONFIG_NAND_FSL_IFC
  86 #endif
  87
  88 #define CONFIG_SYS_NAND_BASE            0x7e800000
  89 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  90
  91 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  92 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  93                                 | CSPR_PORT_SIZE_8      \
  94                                 | CSPR_MSEL_NAND        \
  95                                 | CSPR_V)
  96 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  97 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  98                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  99                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 100                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 101                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 102                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 103                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 104
 105 #define CONFIG_SYS_NAND_ONFI_DETECTION
 106
 107 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 108                                         FTIM0_NAND_TWP(0x18)   | \
 109                                         FTIM0_NAND_TWCHT(0x7) | \
 110                                         FTIM0_NAND_TWH(0xa))
 111 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 112                                         FTIM1_NAND_TWBE(0x39)  | \
 113                                         FTIM1_NAND_TRR(0xe)   | \
 114                                         FTIM1_NAND_TRP(0x18))
 115 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 116                                         FTIM2_NAND_TREH(0xa) | \
 117                                         FTIM2_NAND_TWHRE(0x1e))
 118 #define CONFIG_SYS_NAND_FTIM3           0x0
 119
 120 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 122 #define CONFIG_MTD_NAND_VERIFY_WRITE
 123
 124 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 125
 126 #ifdef CONFIG_NAND_BOOT
 127 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 128 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 129 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 130 #endif
 131
 132 /*
 133  * CPLD
 134  */
 135 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 136 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 137
 138 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 139 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 140                                         CSPR_PORT_SIZE_8 | \
 141                                         CSPR_MSEL_GPCM | \
 142                                         CSPR_V)
 143 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 144 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 145                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 146                                         CSOR_NOR_TRHZ_80)
 147
 148 /* CPLD Timing parameters for IFC GPCM */
 149 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 150                                         FTIM0_GPCM_TEADC(0xf) | \
 151                                         FTIM0_GPCM_TEAHC(0xf))
 152 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 153                                         FTIM1_GPCM_TRAD(0x3f))
 154 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 155                                         FTIM2_GPCM_TCH(0xf) | \
 156                                         FTIM2_GPCM_TWP(0xff))
 157 #define CONFIG_SYS_CPLD_FTIM3           0x0
 158
 159 /* IFC Timing Params */
 160 #ifdef CONFIG_TFABOOT
 161 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 162 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 163 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 164 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 165 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 166 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 167 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 168 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 169
 170 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 171 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 172 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 173 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 174 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 175 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 176 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 177 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 178 #else
 179 #ifdef CONFIG_NAND_BOOT
 180 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 181 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 182 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 183 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 184 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 185 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 186 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 187 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 188
 189 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 190 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 191 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 192 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 193 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 194 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 195 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 196 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 197 #else
 198 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 199 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 200 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 201 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 206
 207 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 208 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 209 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 210 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 211 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 212 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 213 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 214 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 215 #endif
 216 #endif
 217
 218 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 219 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 220 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 221 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 222 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 223 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 224 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 225 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 226
 227 /* EEPROM */
 228 #ifndef SPL_NO_EEPROM
 229 #define CONFIG_SYS_I2C_EEPROM_NXID
 230 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 231 #endif
 232
 233 /*
 234  * Environment
 235  */
 236
 237 /* FMan */
 238 #ifndef SPL_NO_FMAN
 239 #define AQR105_IRQ_MASK                 0x40000000
 240
 241 #ifdef CONFIG_SYS_DPAA_FMAN
 242 #define RGMII_PHY1_ADDR                 0x1
 243 #define RGMII_PHY2_ADDR                 0x2
 244
 245 #define QSGMII_PORT1_PHY_ADDR           0x4
 246 #define QSGMII_PORT2_PHY_ADDR           0x5
 247 #define QSGMII_PORT3_PHY_ADDR           0x6
 248 #define QSGMII_PORT4_PHY_ADDR           0x7
 249
 250 #define FM1_10GEC1_PHY_ADDR             0x1
 251
 252 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 253 #endif
 254 #endif
 255
 256 /* SATA */
 257 #ifndef SPL_NO_SATA
 258 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 259 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 260 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 261                                                 CONFIG_SYS_SCSI_MAX_LUN)
 262 #define SCSI_VEND_ID 0x1b4b
 263 #define SCSI_DEV_ID  0x9170
 264 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 265 #endif
 266
 267 #include <asm/fsl_secure_boot.h>
 268
 269 #endif /* __LS1043ARDB_H__ */