include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12
  13 #define CONFIG_LAYERSCAPE_NS_ACCESS
  14
  15 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  16 /* Physical Memory Map */
  17 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  18
  19 #define CONFIG_SYS_SPD_BUS_NUM          0
  20
  21 #ifndef CONFIG_SPL
  22 #define CONFIG_SYS_DDR_RAW_TIMING
  23 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  24 #endif
  25
  26 #ifdef CONFIG_SD_BOOT
  27 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  28 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  29 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  30 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  31 #endif
  32
  33 /*
  34  * NOR Flash Definitions
  35  */
  36 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  37 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  38 #define CONFIG_SYS_NOR_CSPR                                     \
  39         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  40         CSPR_PORT_SIZE_16                                       | \
  41         CSPR_MSEL_NOR                                           | \
  42         CSPR_V)
  43
  44 /* NOR Flash Timing Params */
  45 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  46                                         CSOR_NOR_TRHZ_80)
  47 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  48                                         FTIM0_NOR_TEADC(0x1) | \
  49                                         FTIM0_NOR_TAVDS(0x0) | \
  50                                         FTIM0_NOR_TEAHC(0xc))
  51 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  52                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  53                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  54 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  55                                         FTIM2_NOR_TCH(0x4) | \
  56                                         FTIM2_NOR_TWPH(0x8) | \
  57                                         FTIM2_NOR_TWP(0x10))
  58 #define CONFIG_SYS_NOR_FTIM3            0
  59 #define CONFIG_SYS_IFC_CCR              0x01000000
  60
  61 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  62 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  63 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  64 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  65
  66 #define CONFIG_SYS_FLASH_EMPTY_INFO
  67 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  68
  69 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  70 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  71
  72 /*
  73  * NAND Flash Definitions
  74  */
  75
  76 #define CONFIG_SYS_NAND_BASE            0x7e800000
  77 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  78
  79 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  80 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  81                                 | CSPR_PORT_SIZE_8      \
  82                                 | CSPR_MSEL_NAND        \
  83                                 | CSPR_V)
  84 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  85 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  86                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  87                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  88                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  89                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  90                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  91                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  92
  93 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  94                                         FTIM0_NAND_TWP(0x18)   | \
  95                                         FTIM0_NAND_TWCHT(0x7) | \
  96                                         FTIM0_NAND_TWH(0xa))
  97 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  98                                         FTIM1_NAND_TWBE(0x39)  | \
  99                                         FTIM1_NAND_TRR(0xe)   | \
 100                                         FTIM1_NAND_TRP(0x18))
 101 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 102                                         FTIM2_NAND_TREH(0xa) | \
 103                                         FTIM2_NAND_TWHRE(0x1e))
 104 #define CONFIG_SYS_NAND_FTIM3           0x0
 105
 106 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 107 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 108 #define CONFIG_MTD_NAND_VERIFY_WRITE
 109
 110 #ifdef CONFIG_NAND_BOOT
 111 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 112 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 113 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 114 #endif
 115
 116 /*
 117  * CPLD
 118  */
 119 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 120 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 121
 122 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 123 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 124                                         CSPR_PORT_SIZE_8 | \
 125                                         CSPR_MSEL_GPCM | \
 126                                         CSPR_V)
 127 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 128 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 129                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 130                                         CSOR_NOR_TRHZ_80)
 131
 132 /* CPLD Timing parameters for IFC GPCM */
 133 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 134                                         FTIM0_GPCM_TEADC(0xf) | \
 135                                         FTIM0_GPCM_TEAHC(0xf))
 136 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 137                                         FTIM1_GPCM_TRAD(0x3f))
 138 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 139                                         FTIM2_GPCM_TCH(0xf) | \
 140                                         FTIM2_GPCM_TWP(0xff))
 141 #define CONFIG_SYS_CPLD_FTIM3           0x0
 142
 143 /* IFC Timing Params */
 144 #ifdef CONFIG_TFABOOT
 145 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 146 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 147 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 148 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 149 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 150 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 151 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 152 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 153
 154 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 155 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 156 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 157 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 158 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 159 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 160 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 161 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 162 #else
 163 #ifdef CONFIG_NAND_BOOT
 164 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 165 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 166 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 167 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 168 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 169 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 170 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 171 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 172
 173 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 174 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 175 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 176 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 177 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 178 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 179 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 180 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 181 #else
 182 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 183 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 184 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 185 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 186 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 187 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 188 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 189 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 190
 191 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 192 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 193 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 194 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 195 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 196 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 197 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 198 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 199 #endif
 200 #endif
 201
 202 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 203 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 204 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 205 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 206 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 207 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 208 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 209 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 210
 211 /* EEPROM */
 212 #ifndef SPL_NO_EEPROM
 213 #define CONFIG_SYS_I2C_EEPROM_NXID
 214 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 215 #endif
 216
 217 /*
 218  * Environment
 219  */
 220
 221 /* FMan */
 222 #ifndef SPL_NO_FMAN
 223 #define AQR105_IRQ_MASK                 0x40000000
 224
 225 #ifdef CONFIG_SYS_DPAA_FMAN
 226 #define RGMII_PHY1_ADDR                 0x1
 227 #define RGMII_PHY2_ADDR                 0x2
 228
 229 #define QSGMII_PORT1_PHY_ADDR           0x4
 230 #define QSGMII_PORT2_PHY_ADDR           0x5
 231 #define QSGMII_PORT3_PHY_ADDR           0x6
 232 #define QSGMII_PORT4_PHY_ADDR           0x7
 233
 234 #define FM1_10GEC1_PHY_ADDR             0x1
 235
 236 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 237 #endif
 238 #endif
 239
 240 /* SATA */
 241 #ifndef SPL_NO_SATA
 242 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 243 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 244 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 245                                                 CONFIG_SYS_SCSI_MAX_LUN)
 246 #define SCSI_VEND_ID 0x1b4b
 247 #define SCSI_DEV_ID  0x9170
 248 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 249 #endif
 250
 251 #include <asm/fsl_secure_boot.h>
 252
 253 #endif /* __LS1043ARDB_H__ */