1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor
6 #ifndef __LS1043ARDB_H__
7 #define __LS1043ARDB_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
14 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
18 * NOR Flash Definitions
20 #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
21 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
22 #define CONFIG_SYS_NOR_CSPR \
23 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
28 /* NOR Flash Timing Params */
29 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
31 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
32 FTIM0_NOR_TEADC(0x1) | \
33 FTIM0_NOR_TAVDS(0x0) | \
35 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
36 FTIM1_NOR_TRAD_NOR(0xb) | \
37 FTIM1_NOR_TSEQRAD_NOR(0x9))
38 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
39 FTIM2_NOR_TCH(0x4) | \
40 FTIM2_NOR_TWPH(0x8) | \
42 #define CONFIG_SYS_NOR_FTIM3 0
43 #define CONFIG_SYS_IFC_CCR 0x01000000
45 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
47 #define CONFIG_SYS_WRITE_SWAPPED_DATA
50 * NAND Flash Definitions
53 #define CONFIG_SYS_NAND_BASE 0x7e800000
54 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
56 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
57 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
61 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
62 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
63 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
64 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
65 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
66 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
67 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
68 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
70 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
71 FTIM0_NAND_TWP(0x18) | \
72 FTIM0_NAND_TWCHT(0x7) | \
74 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
75 FTIM1_NAND_TWBE(0x39) | \
76 FTIM1_NAND_TRR(0xe) | \
78 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
79 FTIM2_NAND_TREH(0xa) | \
80 FTIM2_NAND_TWHRE(0x1e))
81 #define CONFIG_SYS_NAND_FTIM3 0x0
83 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
84 #define CONFIG_SYS_MAX_NAND_DEVICE 1
85 #define CONFIG_MTD_NAND_VERIFY_WRITE
87 #ifdef CONFIG_NAND_BOOT
88 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
94 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
95 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
97 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
98 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
102 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
103 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
104 CSOR_NOR_NOR_MODE_AVD_NOR | \
107 /* CPLD Timing parameters for IFC GPCM */
108 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
109 FTIM0_GPCM_TEADC(0xf) | \
110 FTIM0_GPCM_TEAHC(0xf))
111 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
112 FTIM1_GPCM_TRAD(0x3f))
113 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
114 FTIM2_GPCM_TCH(0xf) | \
115 FTIM2_GPCM_TWP(0xff))
116 #define CONFIG_SYS_CPLD_FTIM3 0x0
118 /* IFC Timing Params */
119 #ifdef CONFIG_TFABOOT
120 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
121 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
122 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
123 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
124 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
125 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
126 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
127 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
129 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
130 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
131 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
132 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
133 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
134 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
135 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
136 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
138 #ifdef CONFIG_NAND_BOOT
139 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
140 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
141 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
142 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
143 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
144 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
145 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
146 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
148 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
149 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
150 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
151 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
152 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
153 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
154 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
155 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
157 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
158 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
159 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
160 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
161 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
162 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
163 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
164 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
166 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
167 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
168 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
169 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
170 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
171 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
172 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
173 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
177 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
178 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
179 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
180 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
181 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
182 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
183 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
184 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
187 #ifndef SPL_NO_EEPROM
188 #define CONFIG_SYS_I2C_EEPROM_NXID
189 #define CONFIG_SYS_EEPROM_BUS_NUM 0
198 #define AQR105_IRQ_MASK 0x40000000
200 #ifdef CONFIG_SYS_DPAA_FMAN
201 #define RGMII_PHY1_ADDR 0x1
202 #define RGMII_PHY2_ADDR 0x2
204 #define QSGMII_PORT1_PHY_ADDR 0x4
205 #define QSGMII_PORT2_PHY_ADDR 0x5
206 #define QSGMII_PORT3_PHY_ADDR 0x6
207 #define QSGMII_PORT4_PHY_ADDR 0x7
209 #define FM1_10GEC1_PHY_ADDR 0x1
215 #define SCSI_VEND_ID 0x1b4b
216 #define SCSI_DEV_ID 0x9170
217 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
220 #include <asm/fsl_secure_boot.h>
222 #endif /* __LS1043ARDB_H__ */