2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043ARDB_H__
8 #define __LS1043ARDB_H__
10 #include "ls1043a_common.h"
12 #if defined(CONFIG_FSL_LS_PPA)
13 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
14 #define SEC_FIRMWARE_ERET_ADDR_REVERT
15 #define CONFIG_ARMV8_PSCI
17 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
18 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
19 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
23 #define CONFIG_DISPLAY_BOARDINFO
25 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
26 #define CONFIG_SYS_TEXT_BASE 0x82000000
28 #define CONFIG_SYS_TEXT_BASE 0x60100000
31 #define CONFIG_SYS_CLK_FREQ 100000000
32 #define CONFIG_DDR_CLK_FREQ 100000000
34 #define CONFIG_LAYERSCAPE_NS_ACCESS
35 #define CONFIG_MISC_INIT_R
37 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
38 /* Physical Memory Map */
39 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
40 #define CONFIG_NR_DRAM_BANKS 2
42 #define CONFIG_SYS_SPD_BUS_NUM 0
44 #define CONFIG_FSL_DDR_BIST
45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #define CONFIG_SYS_DDR_RAW_TIMING
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
50 #ifdef CONFIG_RAMBOOT_PBL
51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
54 #ifdef CONFIG_NAND_BOOT
55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
63 * NOR Flash Definitions
65 #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
67 #define CONFIG_SYS_NOR_CSPR \
68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
73 /* NOR Flash Timing Params */
74 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
76 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
77 FTIM0_NOR_TEADC(0x1) | \
78 FTIM0_NOR_TAVDS(0x0) | \
80 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
81 FTIM1_NOR_TRAD_NOR(0xb) | \
82 FTIM1_NOR_TSEQRAD_NOR(0x9))
83 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
84 FTIM2_NOR_TCH(0x4) | \
85 FTIM2_NOR_TWPH(0x8) | \
87 #define CONFIG_SYS_NOR_FTIM3 0
88 #define CONFIG_SYS_IFC_CCR 0x01000000
90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
91 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
92 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
93 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
95 #define CONFIG_SYS_FLASH_EMPTY_INFO
96 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
98 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
99 #define CONFIG_SYS_WRITE_SWAPPED_DATA
102 * NAND Flash Definitions
104 #define CONFIG_NAND_FSL_IFC
106 #define CONFIG_SYS_NAND_BASE 0x7e800000
107 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
109 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
110 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
114 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
115 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
116 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
117 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
118 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
119 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
120 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
121 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
123 #define CONFIG_SYS_NAND_ONFI_DETECTION
125 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
126 FTIM0_NAND_TWP(0x18) | \
127 FTIM0_NAND_TWCHT(0x7) | \
129 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
130 FTIM1_NAND_TWBE(0x39) | \
131 FTIM1_NAND_TRR(0xe) | \
132 FTIM1_NAND_TRP(0x18))
133 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
134 FTIM2_NAND_TREH(0xa) | \
135 FTIM2_NAND_TWHRE(0x1e))
136 #define CONFIG_SYS_NAND_FTIM3 0x0
138 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
139 #define CONFIG_SYS_MAX_NAND_DEVICE 1
140 #define CONFIG_MTD_NAND_VERIFY_WRITE
141 #define CONFIG_CMD_NAND
143 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
145 #ifdef CONFIG_NAND_BOOT
146 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
147 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
148 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
154 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
155 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
157 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
158 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
162 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
163 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
164 CSOR_NOR_NOR_MODE_AVD_NOR | \
167 /* CPLD Timing parameters for IFC GPCM */
168 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
169 FTIM0_GPCM_TEADC(0xf) | \
170 FTIM0_GPCM_TEAHC(0xf))
171 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
172 FTIM1_GPCM_TRAD(0x3f))
173 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
174 FTIM2_GPCM_TCH(0xf) | \
175 FTIM2_GPCM_TWP(0xff))
176 #define CONFIG_SYS_CPLD_FTIM3 0x0
178 /* IFC Timing Params */
179 #ifdef CONFIG_NAND_BOOT
180 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
181 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
182 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
183 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
184 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
185 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
186 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
187 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
189 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
190 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
191 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
192 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
193 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
194 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
195 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
196 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
199 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
200 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
201 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
202 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
203 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
204 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
205 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
207 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
208 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
209 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
210 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
211 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
212 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
213 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
214 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
217 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
218 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
219 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
220 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
221 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
222 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
223 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
224 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
227 #define CONFIG_ID_EEPROM
228 #define CONFIG_SYS_I2C_EEPROM_NXID
229 #define CONFIG_SYS_EEPROM_BUS_NUM 0
230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
238 #define CONFIG_ENV_OVERWRITE
240 #if defined(CONFIG_NAND_BOOT)
241 #define CONFIG_ENV_IS_IN_NAND
242 #define CONFIG_ENV_SIZE 0x2000
243 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
244 #elif defined(CONFIG_SD_BOOT)
245 #define CONFIG_ENV_OFFSET (1024 * 1024)
246 #define CONFIG_ENV_IS_IN_MMC
247 #define CONFIG_SYS_MMC_ENV_DEV 0
248 #define CONFIG_ENV_SIZE 0x2000
250 #define CONFIG_ENV_IS_IN_FLASH
251 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
252 #define CONFIG_ENV_SECT_SIZE 0x20000
253 #define CONFIG_ENV_SIZE 0x20000
257 #ifdef CONFIG_SYS_DPAA_FMAN
258 #define CONFIG_FMAN_ENET
259 #define CONFIG_PHYLIB
260 #define CONFIG_PHYLIB_10G
261 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
263 #define CONFIG_PHY_VITESSE
264 #define CONFIG_PHY_REALTEK
265 #define CONFIG_PHY_AQUANTIA
266 #define AQR105_IRQ_MASK 0x40000000
268 #define RGMII_PHY1_ADDR 0x1
269 #define RGMII_PHY2_ADDR 0x2
271 #define QSGMII_PORT1_PHY_ADDR 0x4
272 #define QSGMII_PORT2_PHY_ADDR 0x5
273 #define QSGMII_PORT3_PHY_ADDR 0x6
274 #define QSGMII_PORT4_PHY_ADDR 0x7
276 #define FM1_10GEC1_PHY_ADDR 0x1
278 #define CONFIG_ETHPRIME "FM1@DTSEC3"
282 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
283 !defined(CONFIG_QSPI_BOOT)
286 #define CONFIG_SYS_QE_FW_ADDR 0x60600000
289 #define CONFIG_HAS_FSL_XHCI_USB
290 #ifdef CONFIG_HAS_FSL_XHCI_USB
291 #define CONFIG_USB_XHCI_FSL
292 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
293 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
297 #define CONFIG_LIBATA
298 #define CONFIG_SCSI_AHCI
299 #define CONFIG_CMD_SCSI
300 #ifndef CONFIG_CMD_FAT
301 #define CONFIG_CMD_FAT
303 #ifndef CONFIG_CMD_EXT2
304 #define CONFIG_CMD_EXT2
306 #define CONFIG_DOS_PARTITION
307 #define CONFIG_BOARD_LATE_INIT
308 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
309 #define CONFIG_SYS_SCSI_MAX_LUN 2
310 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
311 CONFIG_SYS_SCSI_MAX_LUN)
312 #define SCSI_VEND_ID 0x1b4b
313 #define SCSI_DEV_ID 0x9170
314 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
317 #include <asm/fsl_secure_boot.h>
319 #endif /* __LS1043ARDB_H__ */