include/configs/ls1043ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #if defined(CONFIG_FSL_LS_PPA)
  13 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
  14 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
  15 #define CONFIG_SYS_LS_PPA_FW_ADDR       0x60500000
  16 #endif
  17 #endif
  18
  19 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  20 #define CONFIG_SYS_TEXT_BASE            0x82000000
  21 #else
  22 #define CONFIG_SYS_TEXT_BASE            0x60100000
  23 #endif
  24
  25 #define CONFIG_SYS_CLK_FREQ             100000000
  26 #define CONFIG_DDR_CLK_FREQ             100000000
  27
  28 #define CONFIG_LAYERSCAPE_NS_ACCESS
  29 #define CONFIG_MISC_INIT_R
  30
  31 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  32 /* Physical Memory Map */
  33 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  34 #define CONFIG_NR_DRAM_BANKS            2
  35
  36 #define CONFIG_SYS_SPD_BUS_NUM          0
  37
  38 #define CONFIG_FSL_DDR_BIST
  39 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  40 #define CONFIG_SYS_DDR_RAW_TIMING
  41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  42 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  43
  44 #ifdef CONFIG_RAMBOOT_PBL
  45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  46 #endif
  47
  48 #ifdef CONFIG_NAND_BOOT
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  50 #endif
  51
  52 #ifdef CONFIG_SD_BOOT
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  54 #endif
  55
  56 /*
  57  * NOR Flash Definitions
  58  */
  59 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  60 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  61 #define CONFIG_SYS_NOR_CSPR                                     \
  62         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  63         CSPR_PORT_SIZE_16                                       | \
  64         CSPR_MSEL_NOR                                           | \
  65         CSPR_V)
  66
  67 /* NOR Flash Timing Params */
  68 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  69                                         CSOR_NOR_TRHZ_80)
  70 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  71                                         FTIM0_NOR_TEADC(0x1) | \
  72                                         FTIM0_NOR_TAVDS(0x0) | \
  73                                         FTIM0_NOR_TEAHC(0xc))
  74 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  75                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  76                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  77 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  78                                         FTIM2_NOR_TCH(0x4) | \
  79                                         FTIM2_NOR_TWPH(0x8) | \
  80                                         FTIM2_NOR_TWP(0x10))
  81 #define CONFIG_SYS_NOR_FTIM3            0
  82 #define CONFIG_SYS_IFC_CCR              0x01000000
  83
  84 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  85 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  86 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  87 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  88
  89 #define CONFIG_SYS_FLASH_EMPTY_INFO
  90 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  91
  92 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  93 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  94
  95 /*
  96  * NAND Flash Definitions
  97  */
  98 #define CONFIG_NAND_FSL_IFC
  99
 100 #define CONFIG_SYS_NAND_BASE            0x7e800000
 101 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 102
 103 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 104 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 105                                 | CSPR_PORT_SIZE_8      \
 106                                 | CSPR_MSEL_NAND        \
 107                                 | CSPR_V)
 108 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 109 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 110                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 111                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 112                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 113                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 114                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 115                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 116
 117 #define CONFIG_SYS_NAND_ONFI_DETECTION
 118
 119 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 120                                         FTIM0_NAND_TWP(0x18)   | \
 121                                         FTIM0_NAND_TWCHT(0x7) | \
 122                                         FTIM0_NAND_TWH(0xa))
 123 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 124                                         FTIM1_NAND_TWBE(0x39)  | \
 125                                         FTIM1_NAND_TRR(0xe)   | \
 126                                         FTIM1_NAND_TRP(0x18))
 127 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 128                                         FTIM2_NAND_TREH(0xa) | \
 129                                         FTIM2_NAND_TWHRE(0x1e))
 130 #define CONFIG_SYS_NAND_FTIM3           0x0
 131
 132 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 134 #define CONFIG_MTD_NAND_VERIFY_WRITE
 135 #define CONFIG_CMD_NAND
 136
 137 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 138
 139 #ifdef CONFIG_NAND_BOOT
 140 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 141 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 142 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 143 #endif
 144
 145 /*
 146  * CPLD
 147  */
 148 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 149 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 150
 151 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 152 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 153                                         CSPR_PORT_SIZE_8 | \
 154                                         CSPR_MSEL_GPCM | \
 155                                         CSPR_V)
 156 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 157 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 158                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 159                                         CSOR_NOR_TRHZ_80)
 160
 161 /* CPLD Timing parameters for IFC GPCM */
 162 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 163                                         FTIM0_GPCM_TEADC(0xf) | \
 164                                         FTIM0_GPCM_TEAHC(0xf))
 165 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 166                                         FTIM1_GPCM_TRAD(0x3f))
 167 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 168                                         FTIM2_GPCM_TCH(0xf) | \
 169                                         FTIM2_GPCM_TWP(0xff))
 170 #define CONFIG_SYS_CPLD_FTIM3           0x0
 171
 172 /* IFC Timing Params */
 173 #ifdef CONFIG_NAND_BOOT
 174 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 175 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 176 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 177 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 178 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 179 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 180 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 181 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 182
 183 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 184 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 185 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 186 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 187 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 188 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 189 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 190 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 191 #else
 192 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 193 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 194 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 195 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 196 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 197 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 198 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 199 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 200
 201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 203 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 204 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 205 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 206 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 207 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 208 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 209 #endif
 210
 211 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 212 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 213 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 214 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 215 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 216 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 217 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 218 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 219
 220 /* EEPROM */
 221 #define CONFIG_ID_EEPROM
 222 #define CONFIG_SYS_I2C_EEPROM_NXID
 223 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 224 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 228
 229 /*
 230  * Environment
 231  */
 232 #define CONFIG_ENV_OVERWRITE
 233
 234 #if defined(CONFIG_NAND_BOOT)
 235 #define CONFIG_ENV_IS_IN_NAND
 236 #define CONFIG_ENV_SIZE                 0x2000
 237 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 238 #elif defined(CONFIG_SD_BOOT)
 239 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 240 #define CONFIG_ENV_IS_IN_MMC
 241 #define CONFIG_SYS_MMC_ENV_DEV          0
 242 #define CONFIG_ENV_SIZE                 0x2000
 243 #else
 244 #define CONFIG_ENV_IS_IN_FLASH
 245 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 246 #define CONFIG_ENV_SECT_SIZE            0x20000
 247 #define CONFIG_ENV_SIZE                 0x20000
 248 #endif
 249
 250 /* FMan */
 251 #ifdef CONFIG_SYS_DPAA_FMAN
 252 #define CONFIG_FMAN_ENET
 253 #define CONFIG_PHYLIB
 254 #define CONFIG_PHYLIB_10G
 255 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 256
 257 #define CONFIG_PHY_VITESSE
 258 #define CONFIG_PHY_REALTEK
 259 #define CONFIG_PHY_AQUANTIA
 260 #define AQR105_IRQ_MASK                 0x40000000
 261
 262 #define RGMII_PHY1_ADDR                 0x1
 263 #define RGMII_PHY2_ADDR                 0x2
 264
 265 #define QSGMII_PORT1_PHY_ADDR           0x4
 266 #define QSGMII_PORT2_PHY_ADDR           0x5
 267 #define QSGMII_PORT3_PHY_ADDR           0x6
 268 #define QSGMII_PORT4_PHY_ADDR           0x7
 269
 270 #define FM1_10GEC1_PHY_ADDR             0x1
 271
 272 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 273 #endif
 274
 275 /* QE */
 276 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 277         !defined(CONFIG_QSPI_BOOT)
 278 #define CONFIG_U_QE
 279 #endif
 280 #define CONFIG_SYS_QE_FW_ADDR     0x60600000
 281
 282 /* USB */
 283 #define CONFIG_HAS_FSL_XHCI_USB
 284 #ifdef CONFIG_HAS_FSL_XHCI_USB
 285 #define CONFIG_USB_XHCI_FSL
 286 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
 287 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 288 #endif
 289
 290 /* SATA */
 291 #define CONFIG_LIBATA
 292 #define CONFIG_SCSI_AHCI
 293 #define CONFIG_CMD_SCSI
 294 #ifndef CONFIG_CMD_FAT
 295 #define CONFIG_CMD_FAT
 296 #endif
 297 #ifndef CONFIG_CMD_EXT2
 298 #define CONFIG_CMD_EXT2
 299 #endif
 300 #define CONFIG_DOS_PARTITION
 301 #define CONFIG_BOARD_LATE_INIT
 302 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 303 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 304 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 305                                                 CONFIG_SYS_SCSI_MAX_LUN)
 306 #define SCSI_VEND_ID 0x1b4b
 307 #define SCSI_DEV_ID  0x9170
 308 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 309
 310 #define CONFIG_PARTITION_UUIDS
 311 #define CONFIG_EFI_PARTITION
 312 #define CONFIG_CMD_GPT
 313
 314 #include <asm/fsl_secure_boot.h>
 315
 316 #endif /* __LS1043ARDB_H__ */