include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 /* Physical Memory Map */
  15 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  16
  17 #define CONFIG_SYS_SPD_BUS_NUM          0
  18
  19 #ifndef CONFIG_SPL
  20 #define CONFIG_SYS_DDR_RAW_TIMING
  21 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  22 #endif
  23
  24 #ifdef CONFIG_SD_BOOT
  25 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  26 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  27 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  28 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  29 #endif
  30
  31 /*
  32  * NOR Flash Definitions
  33  */
  34 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  35 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  36 #define CONFIG_SYS_NOR_CSPR                                     \
  37         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  38         CSPR_PORT_SIZE_16                                       | \
  39         CSPR_MSEL_NOR                                           | \
  40         CSPR_V)
  41
  42 /* NOR Flash Timing Params */
  43 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  44                                         CSOR_NOR_TRHZ_80)
  45 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  46                                         FTIM0_NOR_TEADC(0x1) | \
  47                                         FTIM0_NOR_TAVDS(0x0) | \
  48                                         FTIM0_NOR_TEAHC(0xc))
  49 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  50                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  51                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  52 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  53                                         FTIM2_NOR_TCH(0x4) | \
  54                                         FTIM2_NOR_TWPH(0x8) | \
  55                                         FTIM2_NOR_TWP(0x10))
  56 #define CONFIG_SYS_NOR_FTIM3            0
  57 #define CONFIG_SYS_IFC_CCR              0x01000000
  58
  59 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  60 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  61 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  62 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  63
  64 #define CONFIG_SYS_FLASH_EMPTY_INFO
  65 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  66
  67 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  68 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  69
  70 /*
  71  * NAND Flash Definitions
  72  */
  73
  74 #define CONFIG_SYS_NAND_BASE            0x7e800000
  75 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  76
  77 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  78 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  79                                 | CSPR_PORT_SIZE_8      \
  80                                 | CSPR_MSEL_NAND        \
  81                                 | CSPR_V)
  82 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  83 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  84                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  85                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  86                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  87                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  88                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  89                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  90
  91 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  92                                         FTIM0_NAND_TWP(0x18)   | \
  93                                         FTIM0_NAND_TWCHT(0x7) | \
  94                                         FTIM0_NAND_TWH(0xa))
  95 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  96                                         FTIM1_NAND_TWBE(0x39)  | \
  97                                         FTIM1_NAND_TRR(0xe)   | \
  98                                         FTIM1_NAND_TRP(0x18))
  99 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 100                                         FTIM2_NAND_TREH(0xa) | \
 101                                         FTIM2_NAND_TWHRE(0x1e))
 102 #define CONFIG_SYS_NAND_FTIM3           0x0
 103
 104 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 105 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 106 #define CONFIG_MTD_NAND_VERIFY_WRITE
 107
 108 #ifdef CONFIG_NAND_BOOT
 109 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 110 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 111 #endif
 112
 113 /*
 114  * CPLD
 115  */
 116 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 117 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 118
 119 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 120 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 121                                         CSPR_PORT_SIZE_8 | \
 122                                         CSPR_MSEL_GPCM | \
 123                                         CSPR_V)
 124 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 125 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 126                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 127                                         CSOR_NOR_TRHZ_80)
 128
 129 /* CPLD Timing parameters for IFC GPCM */
 130 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 131                                         FTIM0_GPCM_TEADC(0xf) | \
 132                                         FTIM0_GPCM_TEAHC(0xf))
 133 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 134                                         FTIM1_GPCM_TRAD(0x3f))
 135 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 136                                         FTIM2_GPCM_TCH(0xf) | \
 137                                         FTIM2_GPCM_TWP(0xff))
 138 #define CONFIG_SYS_CPLD_FTIM3           0x0
 139
 140 /* IFC Timing Params */
 141 #ifdef CONFIG_TFABOOT
 142 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 143 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 144 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 145 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 146 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 147 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 148 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 149 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 150
 151 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 152 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 153 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 154 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 155 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 156 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 157 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 158 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 159 #else
 160 #ifdef CONFIG_NAND_BOOT
 161 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 162 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 163 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 164 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 165 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 166 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 167 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 168 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 169
 170 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 171 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 172 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 173 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 174 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 175 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 176 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 177 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 178 #else
 179 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 180 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 181 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 182 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 183 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 184 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 185 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 186 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 187
 188 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 189 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 190 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 191 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 192 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 193 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 194 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 195 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 196 #endif
 197 #endif
 198
 199 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 200 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 201 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 202 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 203 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 204 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 205 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 206 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 207
 208 /* EEPROM */
 209 #ifndef SPL_NO_EEPROM
 210 #define CONFIG_SYS_I2C_EEPROM_NXID
 211 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 212 #endif
 213
 214 /*
 215  * Environment
 216  */
 217
 218 /* FMan */
 219 #ifndef SPL_NO_FMAN
 220 #define AQR105_IRQ_MASK                 0x40000000
 221
 222 #ifdef CONFIG_SYS_DPAA_FMAN
 223 #define RGMII_PHY1_ADDR                 0x1
 224 #define RGMII_PHY2_ADDR                 0x2
 225
 226 #define QSGMII_PORT1_PHY_ADDR           0x4
 227 #define QSGMII_PORT2_PHY_ADDR           0x5
 228 #define QSGMII_PORT3_PHY_ADDR           0x6
 229 #define QSGMII_PORT4_PHY_ADDR           0x7
 230
 231 #define FM1_10GEC1_PHY_ADDR             0x1
 232
 233 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 234 #endif
 235 #endif
 236
 237 /* SATA */
 238 #ifndef SPL_NO_SATA
 239 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 240 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 241 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 242                                                 CONFIG_SYS_SCSI_MAX_LUN)
 243 #define SCSI_VEND_ID 0x1b4b
 244 #define SCSI_DEV_ID  0x9170
 245 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 246 #endif
 247
 248 #include <asm/fsl_secure_boot.h>
 249
 250 #endif /* __LS1043ARDB_H__ */