include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  * Copyright 2022 NXP
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 /* Physical Memory Map */
  13
  14 #ifndef CONFIG_SPL
  15 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  16 #endif
  17
  18 /*
  19  * NOR Flash Definitions
  20  */
  21 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  22 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  23 #define CONFIG_SYS_NOR_CSPR                                     \
  24         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  25         CSPR_PORT_SIZE_16                                       | \
  26         CSPR_MSEL_NOR                                           | \
  27         CSPR_V)
  28
  29 /* NOR Flash Timing Params */
  30 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  31                                         CSOR_NOR_TRHZ_80)
  32 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  33                                         FTIM0_NOR_TEADC(0x1) | \
  34                                         FTIM0_NOR_TAVDS(0x0) | \
  35                                         FTIM0_NOR_TEAHC(0xc))
  36 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  37                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  38                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  39 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  40                                         FTIM2_NOR_TCH(0x4) | \
  41                                         FTIM2_NOR_TWPH(0x8) | \
  42                                         FTIM2_NOR_TWP(0x10))
  43 #define CONFIG_SYS_NOR_FTIM3            0
  44 #define CONFIG_SYS_IFC_CCR              0x01000000
  45
  46 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  47
  48 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  49
  50 /*
  51  * NAND Flash Definitions
  52  */
  53
  54 #define CONFIG_SYS_NAND_BASE            0x7e800000
  55 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  56
  57 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  58 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  59                                 | CSPR_PORT_SIZE_8      \
  60                                 | CSPR_MSEL_NAND        \
  61                                 | CSPR_V)
  62 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  63 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  64                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  65                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  66                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  67                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  68                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  69                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  70
  71 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  72                                         FTIM0_NAND_TWP(0x18)   | \
  73                                         FTIM0_NAND_TWCHT(0x7) | \
  74                                         FTIM0_NAND_TWH(0xa))
  75 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  76                                         FTIM1_NAND_TWBE(0x39)  | \
  77                                         FTIM1_NAND_TRR(0xe)   | \
  78                                         FTIM1_NAND_TRP(0x18))
  79 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  80                                         FTIM2_NAND_TREH(0xa) | \
  81                                         FTIM2_NAND_TWHRE(0x1e))
  82 #define CONFIG_SYS_NAND_FTIM3           0x0
  83
  84 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  85 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  86 #define CONFIG_MTD_NAND_VERIFY_WRITE
  87
  88 #ifdef CONFIG_NAND_BOOT
  89 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
  90 #endif
  91
  92 /*
  93  * CPLD
  94  */
  95 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  96 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  97
  98 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
  99 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 100                                         CSPR_PORT_SIZE_8 | \
 101                                         CSPR_MSEL_GPCM | \
 102                                         CSPR_V)
 103 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 104 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 105                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 106                                         CSOR_NOR_TRHZ_80)
 107
 108 /* CPLD Timing parameters for IFC GPCM */
 109 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 110                                         FTIM0_GPCM_TEADC(0xf) | \
 111                                         FTIM0_GPCM_TEAHC(0xf))
 112 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 113                                         FTIM1_GPCM_TRAD(0x3f))
 114 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 115                                         FTIM2_GPCM_TCH(0xf) | \
 116                                         FTIM2_GPCM_TWP(0xff))
 117 #define CONFIG_SYS_CPLD_FTIM3           0x0
 118
 119 /* IFC Timing Params */
 120 #ifdef CONFIG_TFABOOT
 121 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 122 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 123 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 124 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 125 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 126 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 127 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 128 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 129
 130 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 131 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 132 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 133 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 134 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 135 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 136 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 137 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 138 #else
 139 #ifdef CONFIG_NAND_BOOT
 140 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 141 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 142 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 143 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 144 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 145 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 146 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 147 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 148
 149 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 150 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 151 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 152 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 153 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 154 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 155 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 156 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 157 #else
 158 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 159 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 160 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 161 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 162 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 163 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 164 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 165 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 166
 167 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 168 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 169 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 170 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 171 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 172 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 173 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 174 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 175 #endif
 176 #endif
 177
 178 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 179 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 180 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 181 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 182 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 183 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 184 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 185 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 186
 187 /*
 188  * Environment
 189  */
 190
 191 /* FMan */
 192 #ifndef SPL_NO_FMAN
 193 #define AQR105_IRQ_MASK                 0x40000000
 194
 195 #ifdef CONFIG_SYS_DPAA_FMAN
 196 #define RGMII_PHY1_ADDR                 0x1
 197 #define RGMII_PHY2_ADDR                 0x2
 198
 199 #define QSGMII_PORT1_PHY_ADDR           0x4
 200 #define QSGMII_PORT2_PHY_ADDR           0x5
 201 #define QSGMII_PORT3_PHY_ADDR           0x6
 202 #define QSGMII_PORT4_PHY_ADDR           0x7
 203
 204 /* The AQR PHY model and MDIO address differ between board revisions */
 205 #define FM1_10GEC1_PHY_ADDR             0x1 /* AQR105 on boards up to v6.0 */
 206 #define AQR113C_PHY_ADDR                0x8 /* AQR113C on boards v7.0 and up */
 207 #endif
 208 #endif
 209
 210 /* SATA */
 211 #ifndef SPL_NO_SATA
 212 #define SCSI_VEND_ID 0x1b4b
 213 #define SCSI_DEV_ID  0x9170
 214 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 215 #endif
 216
 217 #include <asm/fsl_secure_boot.h>
 218
 219 #endif /* __LS1043ARDB_H__ */