include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  * Copyright 2022 NXP
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 /* Physical Memory Map */
  13
  14 #ifndef CONFIG_SPL
  15 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  16 #endif
  17
  18 /*
  19  * NOR Flash Definitions
  20  */
  21 #define CFG_SYS_NOR_CSPR_EXT            (0x0)
  22 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128*1024*1024)
  23 #define CFG_SYS_NOR_CSPR                                        \
  24         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  25         CSPR_PORT_SIZE_16                                       | \
  26         CSPR_MSEL_NOR                                           | \
  27         CSPR_V)
  28
  29 /* NOR Flash Timing Params */
  30 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  31                                         CSOR_NOR_TRHZ_80)
  32 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x1) | \
  33                                         FTIM0_NOR_TEADC(0x1) | \
  34                                         FTIM0_NOR_TAVDS(0x0) | \
  35                                         FTIM0_NOR_TEAHC(0xc))
  36 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x1c) | \
  37                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  38                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  39 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x1) | \
  40                                         FTIM2_NOR_TCH(0x4) | \
  41                                         FTIM2_NOR_TWPH(0x8) | \
  42                                         FTIM2_NOR_TWP(0x10))
  43 #define CFG_SYS_NOR_FTIM3               0
  44 #define CFG_SYS_IFC_CCR         0x01000000
  45
  46 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE_PHYS }
  47
  48 #define CFG_SYS_WRITE_SWAPPED_DATA
  49
  50 /*
  51  * NAND Flash Definitions
  52  */
  53
  54 #define CFG_SYS_NAND_BASE               0x7e800000
  55 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  56
  57 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  58 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  59                                 | CSPR_PORT_SIZE_8      \
  60                                 | CSPR_MSEL_NAND        \
  61                                 | CSPR_V)
  62 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
  63 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  64                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  65                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  66                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  67                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  68                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  69                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  70
  71 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
  72                                         FTIM0_NAND_TWP(0x18)   | \
  73                                         FTIM0_NAND_TWCHT(0x7) | \
  74                                         FTIM0_NAND_TWH(0xa))
  75 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  76                                         FTIM1_NAND_TWBE(0x39)  | \
  77                                         FTIM1_NAND_TRR(0xe)   | \
  78                                         FTIM1_NAND_TRP(0x18))
  79 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
  80                                         FTIM2_NAND_TREH(0xa) | \
  81                                         FTIM2_NAND_TWHRE(0x1e))
  82 #define CFG_SYS_NAND_FTIM3              0x0
  83
  84 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
  85 #define CONFIG_MTD_NAND_VERIFY_WRITE
  86
  87 #ifdef CONFIG_NAND_BOOT
  88 #define CFG_SYS_NAND_U_BOOT_SIZE        (1024 << 10)
  89 #endif
  90
  91 /*
  92  * CPLD
  93  */
  94 #define CFG_SYS_CPLD_BASE               0x7fb00000
  95 #define CPLD_BASE_PHYS                  CFG_SYS_CPLD_BASE
  96
  97 #define CFG_SYS_CPLD_CSPR_EXT   (0x0)
  98 #define CFG_SYS_CPLD_CSPR               (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  99                                         CSPR_PORT_SIZE_8 | \
 100                                         CSPR_MSEL_GPCM | \
 101                                         CSPR_V)
 102 #define CFG_SYS_CPLD_AMASK              IFC_AMASK(64 * 1024)
 103 #define CFG_SYS_CPLD_CSOR               (CSOR_NOR_ADM_SHIFT(4) | \
 104                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 105                                         CSOR_NOR_TRHZ_80)
 106
 107 /* CPLD Timing parameters for IFC GPCM */
 108 #define CFG_SYS_CPLD_FTIM0              (FTIM0_GPCM_TACSE(0xf) | \
 109                                         FTIM0_GPCM_TEADC(0xf) | \
 110                                         FTIM0_GPCM_TEAHC(0xf))
 111 #define CFG_SYS_CPLD_FTIM1              (FTIM1_GPCM_TACO(0xff) | \
 112                                         FTIM1_GPCM_TRAD(0x3f))
 113 #define CFG_SYS_CPLD_FTIM2              (FTIM2_GPCM_TCS(0xf) | \
 114                                         FTIM2_GPCM_TCH(0xf) | \
 115                                         FTIM2_GPCM_TWP(0xff))
 116 #define CFG_SYS_CPLD_FTIM3              0x0
 117
 118 /* IFC Timing Params */
 119 #ifdef CONFIG_TFABOOT
 120 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR_CSPR_EXT
 121 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 122 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 123 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 124 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 125 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 126 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 127 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 128
 129 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 130 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 131 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 132 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 133 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 134 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 135 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 136 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 137 #else
 138 #ifdef CONFIG_NAND_BOOT
 139 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 140 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 141 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 142 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 143 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 144 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 145 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 146 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 147
 148 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR_CSPR_EXT
 149 #define CFG_SYS_CSPR1           CFG_SYS_NOR_CSPR
 150 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 151 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 152 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 153 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 154 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 155 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 156 #else
 157 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR_CSPR_EXT
 158 #define CFG_SYS_CSPR0           CFG_SYS_NOR_CSPR
 159 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 160 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 161 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 162 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 163 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 164 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 165
 166 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 167 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 168 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 169 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 170 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 171 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 172 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 173 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 174 #endif
 175 #endif
 176
 177 #define CFG_SYS_CSPR2_EXT               CFG_SYS_CPLD_CSPR_EXT
 178 #define CFG_SYS_CSPR2           CFG_SYS_CPLD_CSPR
 179 #define CFG_SYS_AMASK2          CFG_SYS_CPLD_AMASK
 180 #define CFG_SYS_CSOR2           CFG_SYS_CPLD_CSOR
 181 #define CFG_SYS_CS2_FTIM0               CFG_SYS_CPLD_FTIM0
 182 #define CFG_SYS_CS2_FTIM1               CFG_SYS_CPLD_FTIM1
 183 #define CFG_SYS_CS2_FTIM2               CFG_SYS_CPLD_FTIM2
 184 #define CFG_SYS_CS2_FTIM3               CFG_SYS_CPLD_FTIM3
 185
 186 /*
 187  * Environment
 188  */
 189
 190 /* FMan */
 191 #ifndef SPL_NO_FMAN
 192 #define AQR105_IRQ_MASK                 0x40000000
 193
 194 #ifdef CONFIG_SYS_DPAA_FMAN
 195 #define RGMII_PHY1_ADDR                 0x1
 196 #define RGMII_PHY2_ADDR                 0x2
 197
 198 #define QSGMII_PORT1_PHY_ADDR           0x4
 199 #define QSGMII_PORT2_PHY_ADDR           0x5
 200 #define QSGMII_PORT3_PHY_ADDR           0x6
 201 #define QSGMII_PORT4_PHY_ADDR           0x7
 202
 203 /* The AQR PHY model and MDIO address differ between board revisions */
 204 #define FM1_10GEC1_PHY_ADDR             0x1 /* AQR105 on boards up to v6.0 */
 205 #define AQR113C_PHY_ADDR                0x8 /* AQR113C on boards v7.0 and up */
 206 #endif
 207 #endif
 208
 209 /* SATA */
 210 #ifndef SPL_NO_SATA
 211 #define SCSI_VEND_ID 0x1b4b
 212 #define SCSI_DEV_ID  0x9170
 213 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 214 #endif
 215
 216 #include <asm/fsl_secure_boot.h>
 217
 218 #endif /* __LS1043ARDB_H__ */