1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor
6 #ifndef __LS1043ARDB_H__
7 #define __LS1043ARDB_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_SYS_CLK_FREQ 100000000
13 #define CONFIG_LAYERSCAPE_NS_ACCESS
15 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
16 /* Physical Memory Map */
17 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
19 #define CONFIG_SYS_SPD_BUS_NUM 0
22 #define CONFIG_SYS_DDR_RAW_TIMING
23 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
27 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
28 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
29 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
30 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
34 * NOR Flash Definitions
36 #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
37 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
38 #define CONFIG_SYS_NOR_CSPR \
39 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 /* NOR Flash Timing Params */
45 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
47 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
48 FTIM0_NOR_TEADC(0x1) | \
49 FTIM0_NOR_TAVDS(0x0) | \
51 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
52 FTIM1_NOR_TRAD_NOR(0xb) | \
53 FTIM1_NOR_TSEQRAD_NOR(0x9))
54 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
55 FTIM2_NOR_TCH(0x4) | \
56 FTIM2_NOR_TWPH(0x8) | \
58 #define CONFIG_SYS_NOR_FTIM3 0
59 #define CONFIG_SYS_IFC_CCR 0x01000000
61 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
62 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
63 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
64 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
66 #define CONFIG_SYS_FLASH_EMPTY_INFO
67 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
69 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
70 #define CONFIG_SYS_WRITE_SWAPPED_DATA
73 * NAND Flash Definitions
76 #define CONFIG_SYS_NAND_BASE 0x7e800000
77 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
79 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
80 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
84 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
85 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
86 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
87 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
88 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
89 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
90 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
91 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
93 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
94 FTIM0_NAND_TWP(0x18) | \
95 FTIM0_NAND_TWCHT(0x7) | \
97 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
98 FTIM1_NAND_TWBE(0x39) | \
99 FTIM1_NAND_TRR(0xe) | \
100 FTIM1_NAND_TRP(0x18))
101 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
102 FTIM2_NAND_TREH(0xa) | \
103 FTIM2_NAND_TWHRE(0x1e))
104 #define CONFIG_SYS_NAND_FTIM3 0x0
106 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
107 #define CONFIG_SYS_MAX_NAND_DEVICE 1
108 #define CONFIG_MTD_NAND_VERIFY_WRITE
110 #ifdef CONFIG_NAND_BOOT
111 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
112 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
118 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
119 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
121 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
122 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
126 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
127 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
128 CSOR_NOR_NOR_MODE_AVD_NOR | \
131 /* CPLD Timing parameters for IFC GPCM */
132 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
133 FTIM0_GPCM_TEADC(0xf) | \
134 FTIM0_GPCM_TEAHC(0xf))
135 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
136 FTIM1_GPCM_TRAD(0x3f))
137 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
138 FTIM2_GPCM_TCH(0xf) | \
139 FTIM2_GPCM_TWP(0xff))
140 #define CONFIG_SYS_CPLD_FTIM3 0x0
142 /* IFC Timing Params */
143 #ifdef CONFIG_TFABOOT
144 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
145 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
146 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
147 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
148 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
149 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
150 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
151 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
153 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
154 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
155 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
156 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
157 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
158 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
159 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
160 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
162 #ifdef CONFIG_NAND_BOOT
163 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
164 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
165 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
166 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
167 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
168 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
169 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
170 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
172 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
173 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
174 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
175 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
176 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
177 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
178 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
179 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
181 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
182 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
183 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
184 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
185 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
186 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
187 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
188 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
190 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
191 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
192 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
193 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
194 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
195 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
196 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
197 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
201 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
202 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
203 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
204 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
205 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
206 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
207 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
208 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
211 #ifndef SPL_NO_EEPROM
212 #define CONFIG_SYS_I2C_EEPROM_NXID
213 #define CONFIG_SYS_EEPROM_BUS_NUM 0
222 #define AQR105_IRQ_MASK 0x40000000
224 #ifdef CONFIG_SYS_DPAA_FMAN
225 #define RGMII_PHY1_ADDR 0x1
226 #define RGMII_PHY2_ADDR 0x2
228 #define QSGMII_PORT1_PHY_ADDR 0x4
229 #define QSGMII_PORT2_PHY_ADDR 0x5
230 #define QSGMII_PORT3_PHY_ADDR 0x6
231 #define QSGMII_PORT4_PHY_ADDR 0x7
233 #define FM1_10GEC1_PHY_ADDR 0x1
235 #define CONFIG_ETHPRIME "FM1@DTSEC3"
241 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
242 #define CONFIG_SYS_SCSI_MAX_LUN 2
243 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
244 CONFIG_SYS_SCSI_MAX_LUN)
245 #define SCSI_VEND_ID 0x1b4b
246 #define SCSI_DEV_ID 0x9170
247 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
250 #include <asm/fsl_secure_boot.h>
252 #endif /* __LS1043ARDB_H__ */