1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
12 unsigned long get_board_sys_clk(void);
15 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_LAYERSCAPE_NS_ACCESS
21 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
22 /* Physical Memory Map */
23 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
25 #define CONFIG_DDR_SPD
26 #define SPD_EEPROM_ADDRESS 0x51
27 #define CONFIG_SYS_SPD_BUS_NUM 0
29 #define CONFIG_DDR_ECC
31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
32 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
35 #ifdef CONFIG_SYS_DPAA_FMAN
36 #define RGMII_PHY1_ADDR 0x1
37 #define RGMII_PHY2_ADDR 0x2
38 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
39 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
40 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
41 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
42 /* PHY address on QSGMII riser card on slot 1 */
43 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
44 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
45 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
46 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
47 /* PHY address on QSGMII riser card on slot 2 */
48 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
49 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
50 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
51 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
54 #ifdef CONFIG_RAMBOOT_PBL
55 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
58 #ifdef CONFIG_NAND_BOOT
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
63 #ifdef CONFIG_SD_BOOT_QSPI
64 #define CONFIG_SYS_FSL_PBL_RCW \
65 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
73 #define CONFIG_LPUART_32B_REG
77 #define CONFIG_SCSI_AHCI_PLAT
80 #define CONFIG_SYS_I2C_EEPROM_NXID
81 #define CONFIG_SYS_EEPROM_BUS_NUM 0
83 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
85 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
86 #define CONFIG_SYS_SCSI_MAX_LUN 1
87 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
88 CONFIG_SYS_SCSI_MAX_LUN)
93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
94 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
95 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
99 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
100 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
102 CSPR_PORT_SIZE_16 | \
105 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
107 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
109 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
110 FTIM0_NOR_TEADC(0x5) | \
111 FTIM0_NOR_TEAHC(0x5))
112 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
113 FTIM1_NOR_TRAD_NOR(0x1a) | \
114 FTIM1_NOR_TSEQRAD_NOR(0x13))
115 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
116 FTIM2_NOR_TCH(0x4) | \
117 FTIM2_NOR_TWPH(0xe) | \
119 #define CONFIG_SYS_NOR_FTIM3 0
121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
122 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
123 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
124 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
126 #define CONFIG_SYS_FLASH_EMPTY_INFO
127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
128 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
130 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
131 #define CONFIG_SYS_WRITE_SWAPPED_DATA
134 * NAND Flash Definitions
136 #define CONFIG_NAND_FSL_IFC
138 #define CONFIG_SYS_NAND_BASE 0x7e800000
139 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
141 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
143 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
147 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
148 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
149 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
150 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
151 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
152 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
153 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
154 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
156 #define CONFIG_SYS_NAND_ONFI_DETECTION
158 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
159 FTIM0_NAND_TWP(0x18) | \
160 FTIM0_NAND_TWCHT(0x7) | \
162 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
163 FTIM1_NAND_TWBE(0x39) | \
164 FTIM1_NAND_TRR(0xe) | \
165 FTIM1_NAND_TRP(0x18))
166 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
167 FTIM2_NAND_TREH(0xa) | \
168 FTIM2_NAND_TWHRE(0x1e))
169 #define CONFIG_SYS_NAND_FTIM3 0x0
171 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
172 #define CONFIG_SYS_MAX_NAND_DEVICE 1
173 #define CONFIG_MTD_NAND_VERIFY_WRITE
175 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
178 #ifdef CONFIG_NAND_BOOT
179 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
180 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
181 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
184 #if defined(CONFIG_TFABOOT) || \
185 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
186 #define CONFIG_QIXIS_I2C_ACCESS
192 #define CONFIG_FSL_QIXIS
194 #ifdef CONFIG_FSL_QIXIS
195 #define QIXIS_BASE 0x7fb00000
196 #define QIXIS_BASE_PHYS QIXIS_BASE
197 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
198 #define QIXIS_LBMAP_SWITCH 6
199 #define QIXIS_LBMAP_MASK 0x0f
200 #define QIXIS_LBMAP_SHIFT 0
201 #define QIXIS_LBMAP_DFLTBANK 0x00
202 #define QIXIS_LBMAP_ALTBANK 0x04
203 #define QIXIS_LBMAP_NAND 0x09
204 #define QIXIS_LBMAP_SD 0x00
205 #define QIXIS_LBMAP_SD_QSPI 0xff
206 #define QIXIS_LBMAP_QSPI 0xff
207 #define QIXIS_RCW_SRC_NAND 0x106
208 #define QIXIS_RCW_SRC_SD 0x040
209 #define QIXIS_RCW_SRC_QSPI 0x045
210 #define QIXIS_RST_CTL_RESET 0x41
211 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
212 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
213 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
215 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
216 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
220 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
221 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
222 CSOR_NOR_NOR_MODE_AVD_NOR | \
226 * QIXIS Timing parameters for IFC GPCM
228 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
229 FTIM0_GPCM_TEADC(0x20) | \
230 FTIM0_GPCM_TEAHC(0x10))
231 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
232 FTIM1_GPCM_TRAD(0x1f))
233 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
234 FTIM2_GPCM_TCH(0x8) | \
235 FTIM2_GPCM_TWP(0xf0))
236 #define CONFIG_SYS_FPGA_FTIM3 0x0
239 #ifdef CONFIG_TFABOOT
240 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
241 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
242 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
243 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
244 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
245 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
246 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
247 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
248 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
249 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
251 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
252 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
253 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
254 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
255 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
256 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
257 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
258 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
259 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
260 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
261 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
262 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
263 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
264 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
265 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
266 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
267 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
268 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
269 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
270 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
271 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
273 #ifdef CONFIG_NAND_BOOT
274 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
275 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
276 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
277 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
278 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
279 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
280 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
281 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
282 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
284 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
291 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
292 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
293 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
294 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
295 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
296 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
297 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
298 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
299 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
300 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
301 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
302 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
303 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
304 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
305 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
307 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
324 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
325 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
326 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
327 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
328 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
329 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
330 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
331 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
332 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
333 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
334 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
335 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
336 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
337 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
338 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
343 * I2C bus multiplexer
345 #define I2C_MUX_PCA_ADDR_PRI 0x77
346 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
347 #define I2C_RETIMER_ADDR 0x18
348 #define I2C_MUX_CH_DEFAULT 0x8
349 #define I2C_MUX_CH_CH7301 0xC
350 #define I2C_MUX_CH5 0xD
351 #define I2C_MUX_CH7 0xF
353 #define I2C_MUX_CH_VOL_MONITOR 0xa
355 /* Voltage monitor on channel 2*/
356 #define I2C_VOL_MONITOR_ADDR 0x40
357 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
358 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
359 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
361 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
362 #ifndef CONFIG_SPL_BUILD
365 #define CONFIG_VOL_MONITOR_IR36021_SET
366 #define CONFIG_VOL_MONITOR_INA220
367 /* The lowest and highest voltage allowed for LS1043AQDS */
368 #define VDD_MV_MIN 819
369 #define VDD_MV_MAX 1212
372 * Miscellaneous configurable options
375 #define CONFIG_SYS_HZ 1000
377 #define CONFIG_SYS_INIT_SP_OFFSET \
378 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
380 #ifdef CONFIG_SPL_BUILD
381 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
383 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
390 #define CONFIG_CMDLINE_TAG
392 #include <asm/fsl_secure_boot.h>
394 #endif /* __LS1043AQDS_H__ */