1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
12 unsigned long get_board_sys_clk(void);
15 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_LAYERSCAPE_NS_ACCESS
21 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
22 /* Physical Memory Map */
23 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
25 #define SPD_EEPROM_ADDRESS 0x51
26 #define CONFIG_SYS_SPD_BUS_NUM 0
29 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #ifdef CONFIG_SYS_DPAA_FMAN
33 #define RGMII_PHY1_ADDR 0x1
34 #define RGMII_PHY2_ADDR 0x2
35 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
36 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
37 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
38 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
39 /* PHY address on QSGMII riser card on slot 1 */
40 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
41 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
42 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
43 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
44 /* PHY address on QSGMII riser card on slot 2 */
45 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
46 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
47 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
48 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
53 #define CONFIG_LPUART_32B_REG
57 #define CONFIG_SCSI_AHCI_PLAT
60 #define CONFIG_SYS_I2C_EEPROM_NXID
61 #define CONFIG_SYS_EEPROM_BUS_NUM 0
63 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
65 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
66 #define CONFIG_SYS_SCSI_MAX_LUN 1
67 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
68 CONFIG_SYS_SCSI_MAX_LUN)
73 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
74 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
75 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
79 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
80 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
85 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
87 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
89 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
90 FTIM0_NOR_TEADC(0x5) | \
92 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
93 FTIM1_NOR_TRAD_NOR(0x1a) | \
94 FTIM1_NOR_TSEQRAD_NOR(0x13))
95 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
96 FTIM2_NOR_TCH(0x4) | \
97 FTIM2_NOR_TWPH(0xe) | \
99 #define CONFIG_SYS_NOR_FTIM3 0
101 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
102 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
106 #define CONFIG_SYS_FLASH_EMPTY_INFO
107 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
108 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
110 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
111 #define CONFIG_SYS_WRITE_SWAPPED_DATA
114 * NAND Flash Definitions
116 #define CONFIG_NAND_FSL_IFC
118 #define CONFIG_SYS_NAND_BASE 0x7e800000
119 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
121 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
123 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
127 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
128 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
129 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
130 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
131 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
132 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
133 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
134 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
136 #define CONFIG_SYS_NAND_ONFI_DETECTION
138 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
139 FTIM0_NAND_TWP(0x18) | \
140 FTIM0_NAND_TWCHT(0x7) | \
142 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
143 FTIM1_NAND_TWBE(0x39) | \
144 FTIM1_NAND_TRR(0xe) | \
145 FTIM1_NAND_TRP(0x18))
146 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
147 FTIM2_NAND_TREH(0xa) | \
148 FTIM2_NAND_TWHRE(0x1e))
149 #define CONFIG_SYS_NAND_FTIM3 0x0
151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
152 #define CONFIG_SYS_MAX_NAND_DEVICE 1
153 #define CONFIG_MTD_NAND_VERIFY_WRITE
155 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
158 #ifdef CONFIG_NAND_BOOT
159 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
160 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
161 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
164 #if defined(CONFIG_TFABOOT) || \
165 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
166 #define CONFIG_QIXIS_I2C_ACCESS
172 #define CONFIG_FSL_QIXIS
174 #ifdef CONFIG_FSL_QIXIS
175 #define QIXIS_BASE 0x7fb00000
176 #define QIXIS_BASE_PHYS QIXIS_BASE
177 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
178 #define QIXIS_LBMAP_SWITCH 6
179 #define QIXIS_LBMAP_MASK 0x0f
180 #define QIXIS_LBMAP_SHIFT 0
181 #define QIXIS_LBMAP_DFLTBANK 0x00
182 #define QIXIS_LBMAP_ALTBANK 0x04
183 #define QIXIS_LBMAP_NAND 0x09
184 #define QIXIS_LBMAP_SD 0x00
185 #define QIXIS_LBMAP_SD_QSPI 0xff
186 #define QIXIS_LBMAP_QSPI 0xff
187 #define QIXIS_RCW_SRC_NAND 0x106
188 #define QIXIS_RCW_SRC_SD 0x040
189 #define QIXIS_RCW_SRC_QSPI 0x045
190 #define QIXIS_RST_CTL_RESET 0x41
191 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
192 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
193 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
195 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
196 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
200 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
201 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
202 CSOR_NOR_NOR_MODE_AVD_NOR | \
206 * QIXIS Timing parameters for IFC GPCM
208 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
209 FTIM0_GPCM_TEADC(0x20) | \
210 FTIM0_GPCM_TEAHC(0x10))
211 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
212 FTIM1_GPCM_TRAD(0x1f))
213 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
214 FTIM2_GPCM_TCH(0x8) | \
215 FTIM2_GPCM_TWP(0xf0))
216 #define CONFIG_SYS_FPGA_FTIM3 0x0
219 #ifdef CONFIG_TFABOOT
220 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
221 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
222 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
223 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
224 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
225 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
226 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
228 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
229 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
230 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
231 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
232 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
233 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
234 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
235 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
236 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
237 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
238 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
239 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
240 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
241 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
242 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
243 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
244 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
245 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
246 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
247 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
248 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
249 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
250 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
251 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
253 #ifdef CONFIG_NAND_BOOT
254 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
263 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
264 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
271 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
272 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
278 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
279 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
280 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
281 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
282 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
283 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
284 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
285 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
287 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
288 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
289 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
295 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
296 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
297 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
298 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
299 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
300 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
301 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
302 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
303 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
304 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
305 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
306 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
307 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
308 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
309 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
310 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
311 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
312 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
313 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
314 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
315 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
316 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
317 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
318 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
323 * I2C bus multiplexer
325 #define I2C_MUX_PCA_ADDR_PRI 0x77
326 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
327 #define I2C_RETIMER_ADDR 0x18
328 #define I2C_MUX_CH_DEFAULT 0x8
329 #define I2C_MUX_CH_CH7301 0xC
330 #define I2C_MUX_CH5 0xD
331 #define I2C_MUX_CH7 0xF
333 #define I2C_MUX_CH_VOL_MONITOR 0xa
335 /* Voltage monitor on channel 2*/
336 #define I2C_VOL_MONITOR_ADDR 0x40
337 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
338 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
339 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
341 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
342 #ifndef CONFIG_SPL_BUILD
345 #define CONFIG_VOL_MONITOR_IR36021_SET
346 #define CONFIG_VOL_MONITOR_INA220
347 /* The lowest and highest voltage allowed for LS1043AQDS */
348 #define VDD_MV_MIN 819
349 #define VDD_MV_MAX 1212
352 * Miscellaneous configurable options
355 #define CONFIG_SYS_HZ 1000
357 #define CONFIG_SYS_INIT_SP_OFFSET \
358 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
360 #ifdef CONFIG_SPL_BUILD
361 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
370 #define CONFIG_CMDLINE_TAG
372 #include <asm/fsl_secure_boot.h>
374 #endif /* __LS1043AQDS_H__ */