1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 /* Physical Memory Map */
15 #define SPD_EEPROM_ADDRESS 0x51
18 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
21 #ifdef CONFIG_SYS_DPAA_FMAN
22 #define RGMII_PHY1_ADDR 0x1
23 #define RGMII_PHY2_ADDR 0x2
24 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
25 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
26 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
27 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
28 /* PHY address on QSGMII riser card on slot 1 */
29 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
30 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
31 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
32 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
33 /* PHY address on QSGMII riser card on slot 2 */
34 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
35 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
36 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
37 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
43 #define CONFIG_SYS_I2C_EEPROM_NXID
44 #define CONFIG_SYS_EEPROM_BUS_NUM 0
46 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
51 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
52 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
53 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
57 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
58 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
65 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
67 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
68 FTIM0_NOR_TEADC(0x5) | \
70 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
71 FTIM1_NOR_TRAD_NOR(0x1a) | \
72 FTIM1_NOR_TSEQRAD_NOR(0x13))
73 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
74 FTIM2_NOR_TCH(0x4) | \
75 FTIM2_NOR_TWPH(0xe) | \
77 #define CONFIG_SYS_NOR_FTIM3 0
79 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
80 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
81 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
83 #define CONFIG_SYS_FLASH_EMPTY_INFO
84 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
85 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
87 #define CONFIG_SYS_WRITE_SWAPPED_DATA
90 * NAND Flash Definitions
93 #define CONFIG_SYS_NAND_BASE 0x7e800000
94 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
96 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
98 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
102 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
103 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
104 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
105 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
106 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
107 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
108 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
109 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
111 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
112 FTIM0_NAND_TWP(0x18) | \
113 FTIM0_NAND_TWCHT(0x7) | \
115 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
116 FTIM1_NAND_TWBE(0x39) | \
117 FTIM1_NAND_TRR(0xe) | \
118 FTIM1_NAND_TRP(0x18))
119 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
120 FTIM2_NAND_TREH(0xa) | \
121 FTIM2_NAND_TWHRE(0x1e))
122 #define CONFIG_SYS_NAND_FTIM3 0x0
124 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
125 #define CONFIG_SYS_MAX_NAND_DEVICE 1
126 #define CONFIG_MTD_NAND_VERIFY_WRITE
129 #ifdef CONFIG_NAND_BOOT
130 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
133 #if defined(CONFIG_TFABOOT) || \
134 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
141 #ifdef CONFIG_FSL_QIXIS
142 #define QIXIS_BASE 0x7fb00000
143 #define QIXIS_BASE_PHYS QIXIS_BASE
144 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
145 #define QIXIS_LBMAP_SWITCH 6
146 #define QIXIS_LBMAP_MASK 0x0f
147 #define QIXIS_LBMAP_SHIFT 0
148 #define QIXIS_LBMAP_DFLTBANK 0x00
149 #define QIXIS_LBMAP_ALTBANK 0x04
150 #define QIXIS_LBMAP_NAND 0x09
151 #define QIXIS_LBMAP_SD 0x00
152 #define QIXIS_LBMAP_SD_QSPI 0xff
153 #define QIXIS_LBMAP_QSPI 0xff
154 #define QIXIS_RCW_SRC_NAND 0x106
155 #define QIXIS_RCW_SRC_SD 0x040
156 #define QIXIS_RCW_SRC_QSPI 0x045
157 #define QIXIS_RST_CTL_RESET 0x41
158 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
159 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
160 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
162 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
163 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
167 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
168 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
169 CSOR_NOR_NOR_MODE_AVD_NOR | \
173 * QIXIS Timing parameters for IFC GPCM
175 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
176 FTIM0_GPCM_TEADC(0x20) | \
177 FTIM0_GPCM_TEAHC(0x10))
178 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
179 FTIM1_GPCM_TRAD(0x1f))
180 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
181 FTIM2_GPCM_TCH(0x8) | \
182 FTIM2_GPCM_TWP(0xf0))
183 #define CONFIG_SYS_FPGA_FTIM3 0x0
186 #ifdef CONFIG_TFABOOT
187 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
188 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
189 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
190 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
191 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
192 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
193 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
194 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
195 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
196 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
198 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
199 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
200 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
201 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
202 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
203 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
204 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
205 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
206 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
207 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
208 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
209 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
210 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
211 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
212 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
213 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
214 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
215 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
216 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
217 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
218 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
220 #ifdef CONFIG_NAND_BOOT
221 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
225 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
226 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
227 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
228 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
229 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
230 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
231 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
232 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
233 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
234 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
235 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
236 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
237 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
238 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
239 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
240 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
241 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
242 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
243 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
244 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
245 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
246 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
247 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
248 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
249 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
250 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
251 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
252 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
254 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
255 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
256 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
257 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
258 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
259 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
260 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
261 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
262 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
263 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
264 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
271 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
272 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
273 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
274 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
275 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
276 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
277 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
278 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
279 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
280 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
281 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
282 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
283 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
284 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
285 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
290 * I2C bus multiplexer
292 #define I2C_MUX_PCA_ADDR_PRI 0x77
293 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
294 #define I2C_RETIMER_ADDR 0x18
295 #define I2C_MUX_CH_DEFAULT 0x8
296 #define I2C_MUX_CH_CH7301 0xC
297 #define I2C_MUX_CH5 0xD
298 #define I2C_MUX_CH7 0xF
300 #define I2C_MUX_CH_VOL_MONITOR 0xa
302 /* Voltage monitor on channel 2*/
303 #define I2C_VOL_MONITOR_ADDR 0x40
304 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
305 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
306 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
308 /* The lowest and highest voltage allowed for LS1043AQDS */
309 #define VDD_MV_MIN 819
310 #define VDD_MV_MAX 1212
313 * Miscellaneous configurable options
320 #include <asm/fsl_secure_boot.h>
322 #endif /* __LS1043AQDS_H__ */