1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
12 unsigned long get_board_sys_clk(void);
13 unsigned long get_board_ddr_clk(void);
16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
24 /* Physical Memory Map */
25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_DDR_SPD
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
37 #ifdef CONFIG_SYS_DPAA_FMAN
38 #define RGMII_PHY1_ADDR 0x1
39 #define RGMII_PHY2_ADDR 0x2
40 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
41 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
42 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
43 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
44 /* PHY address on QSGMII riser card on slot 1 */
45 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
46 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
47 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
48 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
49 /* PHY address on QSGMII riser card on slot 2 */
50 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
51 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
52 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
53 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
56 #ifdef CONFIG_RAMBOOT_PBL
57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
60 #ifdef CONFIG_NAND_BOOT
61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
65 #ifdef CONFIG_SD_BOOT_QSPI
66 #define CONFIG_SYS_FSL_PBL_RCW \
67 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
75 #define CONFIG_LPUART_32B_REG
79 #define CONFIG_SCSI_AHCI_PLAT
82 #define CONFIG_SYS_I2C_EEPROM_NXID
83 #define CONFIG_SYS_EEPROM_BUS_NUM 0
85 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
87 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
88 #define CONFIG_SYS_SCSI_MAX_LUN 1
89 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
90 CONFIG_SYS_SCSI_MAX_LUN)
95 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
96 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
97 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
101 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
102 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
104 CSPR_PORT_SIZE_16 | \
107 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
109 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
111 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
112 FTIM0_NOR_TEADC(0x5) | \
113 FTIM0_NOR_TEAHC(0x5))
114 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
115 FTIM1_NOR_TRAD_NOR(0x1a) | \
116 FTIM1_NOR_TSEQRAD_NOR(0x13))
117 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
118 FTIM2_NOR_TCH(0x4) | \
119 FTIM2_NOR_TWPH(0xe) | \
121 #define CONFIG_SYS_NOR_FTIM3 0
123 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
124 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
125 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
126 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
128 #define CONFIG_SYS_FLASH_EMPTY_INFO
129 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
130 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
132 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
133 #define CONFIG_SYS_WRITE_SWAPPED_DATA
136 * NAND Flash Definitions
138 #define CONFIG_NAND_FSL_IFC
140 #define CONFIG_SYS_NAND_BASE 0x7e800000
141 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
143 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
145 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
149 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
150 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
151 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
152 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
153 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
154 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
155 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
156 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
158 #define CONFIG_SYS_NAND_ONFI_DETECTION
160 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
161 FTIM0_NAND_TWP(0x18) | \
162 FTIM0_NAND_TWCHT(0x7) | \
164 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
165 FTIM1_NAND_TWBE(0x39) | \
166 FTIM1_NAND_TRR(0xe) | \
167 FTIM1_NAND_TRP(0x18))
168 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
169 FTIM2_NAND_TREH(0xa) | \
170 FTIM2_NAND_TWHRE(0x1e))
171 #define CONFIG_SYS_NAND_FTIM3 0x0
173 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
174 #define CONFIG_SYS_MAX_NAND_DEVICE 1
175 #define CONFIG_MTD_NAND_VERIFY_WRITE
177 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
180 #ifdef CONFIG_NAND_BOOT
181 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
182 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
183 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
186 #if defined(CONFIG_TFABOOT) || \
187 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
188 #define CONFIG_QIXIS_I2C_ACCESS
194 #define CONFIG_FSL_QIXIS
196 #ifdef CONFIG_FSL_QIXIS
197 #define QIXIS_BASE 0x7fb00000
198 #define QIXIS_BASE_PHYS QIXIS_BASE
199 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
200 #define QIXIS_LBMAP_SWITCH 6
201 #define QIXIS_LBMAP_MASK 0x0f
202 #define QIXIS_LBMAP_SHIFT 0
203 #define QIXIS_LBMAP_DFLTBANK 0x00
204 #define QIXIS_LBMAP_ALTBANK 0x04
205 #define QIXIS_LBMAP_NAND 0x09
206 #define QIXIS_LBMAP_SD 0x00
207 #define QIXIS_LBMAP_SD_QSPI 0xff
208 #define QIXIS_LBMAP_QSPI 0xff
209 #define QIXIS_RCW_SRC_NAND 0x106
210 #define QIXIS_RCW_SRC_SD 0x040
211 #define QIXIS_RCW_SRC_QSPI 0x045
212 #define QIXIS_RST_CTL_RESET 0x41
213 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
214 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
215 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
217 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
218 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
222 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
223 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
224 CSOR_NOR_NOR_MODE_AVD_NOR | \
228 * QIXIS Timing parameters for IFC GPCM
230 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
231 FTIM0_GPCM_TEADC(0x20) | \
232 FTIM0_GPCM_TEAHC(0x10))
233 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
234 FTIM1_GPCM_TRAD(0x1f))
235 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
236 FTIM2_GPCM_TCH(0x8) | \
237 FTIM2_GPCM_TWP(0xf0))
238 #define CONFIG_SYS_FPGA_FTIM3 0x0
241 #ifdef CONFIG_TFABOOT
242 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
243 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
246 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
247 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
248 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
249 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
250 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
252 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
253 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
254 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
255 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
256 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
257 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
258 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
259 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
260 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
261 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
262 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
263 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
264 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
265 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
266 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
267 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
268 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
269 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
270 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
271 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
272 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
273 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
275 #ifdef CONFIG_NAND_BOOT
276 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
277 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
278 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
279 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
280 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
281 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
282 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
283 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
284 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
285 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
286 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
293 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
294 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
300 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
301 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
302 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
303 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
304 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
305 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
306 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
307 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
309 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
310 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
311 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
312 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
313 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
314 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
315 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
316 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
317 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
318 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
319 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
325 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
326 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
327 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
328 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
329 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
330 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
331 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
332 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
333 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
334 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
335 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
336 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
337 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
338 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
339 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
340 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
345 * I2C bus multiplexer
347 #define I2C_MUX_PCA_ADDR_PRI 0x77
348 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
349 #define I2C_RETIMER_ADDR 0x18
350 #define I2C_MUX_CH_DEFAULT 0x8
351 #define I2C_MUX_CH_CH7301 0xC
352 #define I2C_MUX_CH5 0xD
353 #define I2C_MUX_CH7 0xF
355 #define I2C_MUX_CH_VOL_MONITOR 0xa
357 /* Voltage monitor on channel 2*/
358 #define I2C_VOL_MONITOR_ADDR 0x40
359 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
360 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
361 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
363 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
364 #ifndef CONFIG_SPL_BUILD
367 #define CONFIG_VOL_MONITOR_IR36021_SET
368 #define CONFIG_VOL_MONITOR_INA220
369 /* The lowest and highest voltage allowed for LS1043AQDS */
370 #define VDD_MV_MIN 819
371 #define VDD_MV_MAX 1212
374 * Miscellaneous configurable options
377 #define CONFIG_SYS_HZ 1000
379 #define CONFIG_SYS_INIT_SP_OFFSET \
380 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
382 #ifdef CONFIG_SPL_BUILD
383 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
385 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
392 #define CONFIG_CMDLINE_TAG
394 #include <asm/fsl_secure_boot.h>
396 #endif /* __LS1043AQDS_H__ */