include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 #endif
  14
  15 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  16
  17 #define CONFIG_SKIP_LOWLEVEL_INIT
  18
  19 #define CONFIG_LAYERSCAPE_NS_ACCESS
  20
  21 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  22 /* Physical Memory Map */
  23 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  24
  25 #define SPD_EEPROM_ADDRESS              0x51
  26 #define CONFIG_SYS_SPD_BUS_NUM          0
  27
  28 #ifdef CONFIG_DDR_ECC
  29 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  30 #endif
  31
  32 #ifdef CONFIG_SYS_DPAA_FMAN
  33 #define RGMII_PHY1_ADDR         0x1
  34 #define RGMII_PHY2_ADDR         0x2
  35 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  36 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  37 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  38 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  39 /* PHY address on QSGMII riser card on slot 1 */
  40 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  41 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  42 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  43 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  44 /* PHY address on QSGMII riser card on slot 2 */
  45 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  46 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  47 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  48 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  49 #endif
  50
  51 #ifdef CONFIG_RAMBOOT_PBL
  52 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  53 #endif
  54
  55 #ifdef CONFIG_NAND_BOOT
  56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  57 #endif
  58
  59 #ifdef CONFIG_SD_BOOT
  60 #ifdef CONFIG_SD_BOOT_QSPI
  61 #define CONFIG_SYS_FSL_PBL_RCW \
  62         board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  63 #else
  64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  65 #endif
  66 #endif
  67
  68 /* LPUART */
  69 #ifdef CONFIG_LPUART
  70 #define CONFIG_LPUART_32B_REG
  71 #endif
  72
  73 /* SATA */
  74 #define CONFIG_SCSI_AHCI_PLAT
  75
  76 /* EEPROM */
  77 #define CONFIG_SYS_I2C_EEPROM_NXID
  78 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  79
  80 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  81
  82 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  83 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  84 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  85                                                 CONFIG_SYS_SCSI_MAX_LUN)
  86
  87 /*
  88  * IFC Definitions
  89  */
  90 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  91 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  92 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  93                                 CSPR_PORT_SIZE_16 | \
  94                                 CSPR_MSEL_NOR | \
  95                                 CSPR_V)
  96 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  97 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  98                                 + 0x8000000) | \
  99                                 CSPR_PORT_SIZE_16 | \
 100                                 CSPR_MSEL_NOR | \
 101                                 CSPR_V)
 102 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 103
 104 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 105                                         CSOR_NOR_TRHZ_80)
 106 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 107                                         FTIM0_NOR_TEADC(0x5) | \
 108                                         FTIM0_NOR_TEAHC(0x5))
 109 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 110                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 111                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 112 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 113                                         FTIM2_NOR_TCH(0x4) | \
 114                                         FTIM2_NOR_TWPH(0xe) | \
 115                                         FTIM2_NOR_TWP(0x1c))
 116 #define CONFIG_SYS_NOR_FTIM3            0
 117
 118 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 119 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 121 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 122
 123 #define CONFIG_SYS_FLASH_EMPTY_INFO
 124 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 125                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 126
 127 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 128 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 129
 130 /*
 131  * NAND Flash Definitions
 132  */
 133 #define CONFIG_NAND_FSL_IFC
 134
 135 #define CONFIG_SYS_NAND_BASE            0x7e800000
 136 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 137
 138 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 139
 140 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 141                                 | CSPR_PORT_SIZE_8      \
 142                                 | CSPR_MSEL_NAND        \
 143                                 | CSPR_V)
 144 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 145 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 146                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 147                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 148                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 149                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 150                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 151                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 152
 153 #define CONFIG_SYS_NAND_ONFI_DETECTION
 154
 155 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 156                                         FTIM0_NAND_TWP(0x18)   | \
 157                                         FTIM0_NAND_TWCHT(0x7) | \
 158                                         FTIM0_NAND_TWH(0xa))
 159 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 160                                         FTIM1_NAND_TWBE(0x39)  | \
 161                                         FTIM1_NAND_TRR(0xe)   | \
 162                                         FTIM1_NAND_TRP(0x18))
 163 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 164                                         FTIM2_NAND_TREH(0xa) | \
 165                                         FTIM2_NAND_TWHRE(0x1e))
 166 #define CONFIG_SYS_NAND_FTIM3           0x0
 167
 168 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 169 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 170 #define CONFIG_MTD_NAND_VERIFY_WRITE
 171
 172 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 173 #endif
 174
 175 #ifdef CONFIG_NAND_BOOT
 176 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 177 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 178 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 179 #endif
 180
 181 #if defined(CONFIG_TFABOOT) || \
 182         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 183 #define CONFIG_QIXIS_I2C_ACCESS
 184 #endif
 185
 186 /*
 187  * QIXIS Definitions
 188  */
 189 #define CONFIG_FSL_QIXIS
 190
 191 #ifdef CONFIG_FSL_QIXIS
 192 #define QIXIS_BASE                      0x7fb00000
 193 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 194 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 195 #define QIXIS_LBMAP_SWITCH              6
 196 #define QIXIS_LBMAP_MASK                0x0f
 197 #define QIXIS_LBMAP_SHIFT               0
 198 #define QIXIS_LBMAP_DFLTBANK            0x00
 199 #define QIXIS_LBMAP_ALTBANK             0x04
 200 #define QIXIS_LBMAP_NAND                0x09
 201 #define QIXIS_LBMAP_SD                  0x00
 202 #define QIXIS_LBMAP_SD_QSPI             0xff
 203 #define QIXIS_LBMAP_QSPI                0xff
 204 #define QIXIS_RCW_SRC_NAND              0x106
 205 #define QIXIS_RCW_SRC_SD                0x040
 206 #define QIXIS_RCW_SRC_QSPI              0x045
 207 #define QIXIS_RST_CTL_RESET             0x41
 208 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 209 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 210 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 211
 212 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 213 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 214                                         CSPR_PORT_SIZE_8 | \
 215                                         CSPR_MSEL_GPCM | \
 216                                         CSPR_V)
 217 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 218 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 219                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 220                                         CSOR_NOR_TRHZ_80)
 221
 222 /*
 223  * QIXIS Timing parameters for IFC GPCM
 224  */
 225 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 226                                         FTIM0_GPCM_TEADC(0x20) | \
 227                                         FTIM0_GPCM_TEAHC(0x10))
 228 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 229                                         FTIM1_GPCM_TRAD(0x1f))
 230 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 231                                         FTIM2_GPCM_TCH(0x8) | \
 232                                         FTIM2_GPCM_TWP(0xf0))
 233 #define CONFIG_SYS_FPGA_FTIM3           0x0
 234 #endif
 235
 236 #ifdef CONFIG_TFABOOT
 237 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 238 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 239 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 240 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 241 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 242 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 243 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 244 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 245 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 246 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 247 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 248 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 249 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 250 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 251 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 252 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 253 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 254 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 255 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 256 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 257 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 258 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 259 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 260 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 261 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 262 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 263 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 264 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 265 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 266 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 267 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 268 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 269 #else
 270 #ifdef CONFIG_NAND_BOOT
 271 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 272 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 273 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 274 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 275 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 276 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 277 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 278 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 279 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 280 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 281 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 295 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 296 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 297 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 298 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 299 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 300 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 301 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 302 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 303 #else
 304 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 305 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 306 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 307 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 308 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 309 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 310 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 311 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 312 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 313 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 314 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 315 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 316 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 317 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 318 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 319 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 320 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 321 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 322 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 323 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 324 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 325 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 326 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 327 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 328 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 329 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 330 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 331 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 332 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 333 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 334 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 335 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 336 #endif
 337 #endif
 338
 339 /*
 340  * I2C bus multiplexer
 341  */
 342 #define I2C_MUX_PCA_ADDR_PRI            0x77
 343 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 344 #define I2C_RETIMER_ADDR                0x18
 345 #define I2C_MUX_CH_DEFAULT              0x8
 346 #define I2C_MUX_CH_CH7301               0xC
 347 #define I2C_MUX_CH5                     0xD
 348 #define I2C_MUX_CH7                     0xF
 349
 350 #define I2C_MUX_CH_VOL_MONITOR 0xa
 351
 352 /* Voltage monitor on channel 2*/
 353 #define I2C_VOL_MONITOR_ADDR           0x40
 354 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 355 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 356 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 357
 358 #define CONFIG_VID_FLS_ENV              "ls1043aqds_vdd_mv"
 359 #ifndef CONFIG_SPL_BUILD
 360 #define CONFIG_VID
 361 #endif
 362 #define CONFIG_VOL_MONITOR_IR36021_SET
 363 #define CONFIG_VOL_MONITOR_INA220
 364 /* The lowest and highest voltage allowed for LS1043AQDS */
 365 #define VDD_MV_MIN                      819
 366 #define VDD_MV_MAX                      1212
 367
 368 /*
 369  * Miscellaneous configurable options
 370  */
 371
 372 #define CONFIG_SYS_HZ                   1000
 373
 374 #define CONFIG_SYS_INIT_SP_OFFSET \
 375         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 376
 377 #ifdef CONFIG_SPL_BUILD
 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 379 #else
 380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 381 #endif
 382
 383 /*
 384  * Environment
 385  */
 386
 387 #define CONFIG_CMDLINE_TAG
 388
 389 #include <asm/fsl_secure_boot.h>
 390
 391 #endif /* __LS1043AQDS_H__ */