include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 /* Physical Memory Map */
  14
  15 #define SPD_EEPROM_ADDRESS              0x51
  16 #define CONFIG_SYS_SPD_BUS_NUM          0
  17
  18 #ifdef CONFIG_DDR_ECC
  19 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  20 #endif
  21
  22 #ifdef CONFIG_SYS_DPAA_FMAN
  23 #define RGMII_PHY1_ADDR         0x1
  24 #define RGMII_PHY2_ADDR         0x2
  25 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  26 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  27 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  28 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  29 /* PHY address on QSGMII riser card on slot 1 */
  30 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  31 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  32 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  33 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  34 /* PHY address on QSGMII riser card on slot 2 */
  35 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  36 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  37 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  38 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  39 #endif
  40
  41 /* SATA */
  42
  43 /* EEPROM */
  44 #define CONFIG_SYS_I2C_EEPROM_NXID
  45 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  46
  47 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  48
  49 /*
  50  * IFC Definitions
  51  */
  52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  53 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  54 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  55                                 CSPR_PORT_SIZE_16 | \
  56                                 CSPR_MSEL_NOR | \
  57                                 CSPR_V)
  58 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  59 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  60                                 + 0x8000000) | \
  61                                 CSPR_PORT_SIZE_16 | \
  62                                 CSPR_MSEL_NOR | \
  63                                 CSPR_V)
  64 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  65
  66 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  67                                         CSOR_NOR_TRHZ_80)
  68 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  69                                         FTIM0_NOR_TEADC(0x5) | \
  70                                         FTIM0_NOR_TEAHC(0x5))
  71 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  72                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  73                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  74 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  75                                         FTIM2_NOR_TCH(0x4) | \
  76                                         FTIM2_NOR_TWPH(0xe) | \
  77                                         FTIM2_NOR_TWP(0x1c))
  78 #define CONFIG_SYS_NOR_FTIM3            0
  79
  80 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  81 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  82 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  83
  84 #define CONFIG_SYS_FLASH_EMPTY_INFO
  85 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  86                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  87
  88 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  89
  90 /*
  91  * NAND Flash Definitions
  92  */
  93
  94 #define CONFIG_SYS_NAND_BASE            0x7e800000
  95 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  96
  97 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  98
  99 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 100                                 | CSPR_PORT_SIZE_8      \
 101                                 | CSPR_MSEL_NAND        \
 102                                 | CSPR_V)
 103 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 104 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 105                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 106                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 107                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 108                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 109                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 110                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 111
 112 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 113                                         FTIM0_NAND_TWP(0x18)   | \
 114                                         FTIM0_NAND_TWCHT(0x7) | \
 115                                         FTIM0_NAND_TWH(0xa))
 116 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 117                                         FTIM1_NAND_TWBE(0x39)  | \
 118                                         FTIM1_NAND_TRR(0xe)   | \
 119                                         FTIM1_NAND_TRP(0x18))
 120 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 121                                         FTIM2_NAND_TREH(0xa) | \
 122                                         FTIM2_NAND_TWHRE(0x1e))
 123 #define CONFIG_SYS_NAND_FTIM3           0x0
 124
 125 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 126 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 127 #define CONFIG_MTD_NAND_VERIFY_WRITE
 128 #endif
 129
 130 #ifdef CONFIG_NAND_BOOT
 131 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 132 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 133 #endif
 134
 135 #if defined(CONFIG_TFABOOT) || \
 136         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 137 #define CONFIG_QIXIS_I2C_ACCESS
 138 #endif
 139
 140 /*
 141  * QIXIS Definitions
 142  */
 143 #define CONFIG_FSL_QIXIS
 144
 145 #ifdef CONFIG_FSL_QIXIS
 146 #define QIXIS_BASE                      0x7fb00000
 147 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 148 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 149 #define QIXIS_LBMAP_SWITCH              6
 150 #define QIXIS_LBMAP_MASK                0x0f
 151 #define QIXIS_LBMAP_SHIFT               0
 152 #define QIXIS_LBMAP_DFLTBANK            0x00
 153 #define QIXIS_LBMAP_ALTBANK             0x04
 154 #define QIXIS_LBMAP_NAND                0x09
 155 #define QIXIS_LBMAP_SD                  0x00
 156 #define QIXIS_LBMAP_SD_QSPI             0xff
 157 #define QIXIS_LBMAP_QSPI                0xff
 158 #define QIXIS_RCW_SRC_NAND              0x106
 159 #define QIXIS_RCW_SRC_SD                0x040
 160 #define QIXIS_RCW_SRC_QSPI              0x045
 161 #define QIXIS_RST_CTL_RESET             0x41
 162 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 163 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 164 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 165
 166 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 167 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 168                                         CSPR_PORT_SIZE_8 | \
 169                                         CSPR_MSEL_GPCM | \
 170                                         CSPR_V)
 171 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 172 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 173                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 174                                         CSOR_NOR_TRHZ_80)
 175
 176 /*
 177  * QIXIS Timing parameters for IFC GPCM
 178  */
 179 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 180                                         FTIM0_GPCM_TEADC(0x20) | \
 181                                         FTIM0_GPCM_TEAHC(0x10))
 182 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 183                                         FTIM1_GPCM_TRAD(0x1f))
 184 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 185                                         FTIM2_GPCM_TCH(0x8) | \
 186                                         FTIM2_GPCM_TWP(0xf0))
 187 #define CONFIG_SYS_FPGA_FTIM3           0x0
 188 #endif
 189
 190 #ifdef CONFIG_TFABOOT
 191 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 193 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 194 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 195 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 196 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 197 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 198 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 199 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 200 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 201 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 202 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 203 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 204 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 205 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 206 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 207 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 208 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 209 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 210 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 211 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 212 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 213 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 214 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 215 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 216 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 217 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 218 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 219 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 220 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 221 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 222 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 223 #else
 224 #ifdef CONFIG_NAND_BOOT
 225 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 226 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 227 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 228 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 229 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 230 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 231 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 232 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 233 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 234 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 235 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 236 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 237 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 238 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 239 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 240 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 241 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 242 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 243 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 244 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 245 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 246 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 247 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 248 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 249 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 250 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 251 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 252 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 253 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 254 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 255 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 256 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 257 #else
 258 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 259 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 260 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 261 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 262 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 263 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 264 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 265 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 266 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 267 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 268 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 269 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 270 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 271 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 272 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 273 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 274 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 275 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 276 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 277 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 278 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 279 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 280 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 281 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 282 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 283 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 284 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 285 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 286 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 287 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 288 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 289 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 290 #endif
 291 #endif
 292
 293 /*
 294  * I2C bus multiplexer
 295  */
 296 #define I2C_MUX_PCA_ADDR_PRI            0x77
 297 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 298 #define I2C_RETIMER_ADDR                0x18
 299 #define I2C_MUX_CH_DEFAULT              0x8
 300 #define I2C_MUX_CH_CH7301               0xC
 301 #define I2C_MUX_CH5                     0xD
 302 #define I2C_MUX_CH7                     0xF
 303
 304 #define I2C_MUX_CH_VOL_MONITOR 0xa
 305
 306 /* Voltage monitor on channel 2*/
 307 #define I2C_VOL_MONITOR_ADDR           0x40
 308 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 309 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 310 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 311
 312 /* The lowest and highest voltage allowed for LS1043AQDS */
 313 #define VDD_MV_MIN                      819
 314 #define VDD_MV_MAX                      1212
 315
 316 /*
 317  * Miscellaneous configurable options
 318  */
 319
 320 #define CONFIG_SYS_INIT_SP_OFFSET \
 321         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 322
 323 /*
 324  * Environment
 325  */
 326
 327 #include <asm/fsl_secure_boot.h>
 328
 329 #endif /* __LS1043AQDS_H__ */