1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 1 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
41 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
42 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
43 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
47 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
48 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
53 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
55 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
57 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
58 FTIM0_NOR_TEADC(0x5) | \
60 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
61 FTIM1_NOR_TRAD_NOR(0x1a) | \
62 FTIM1_NOR_TSEQRAD_NOR(0x13))
63 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
64 FTIM2_NOR_TCH(0x4) | \
65 FTIM2_NOR_TWPH(0xe) | \
67 #define CFG_SYS_NOR_FTIM3 0
69 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
70 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
72 #define CONFIG_SYS_WRITE_SWAPPED_DATA
75 * NAND Flash Definitions
78 #define CFG_SYS_NAND_BASE 0x7e800000
79 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
81 #define CFG_SYS_NAND_CSPR_EXT (0x0)
83 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
87 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
88 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
89 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
90 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
91 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
92 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
93 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
94 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
96 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
97 FTIM0_NAND_TWP(0x18) | \
98 FTIM0_NAND_TWCHT(0x7) | \
100 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
101 FTIM1_NAND_TWBE(0x39) | \
102 FTIM1_NAND_TRR(0xe) | \
103 FTIM1_NAND_TRP(0x18))
104 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
105 FTIM2_NAND_TREH(0xa) | \
106 FTIM2_NAND_TWHRE(0x1e))
107 #define CFG_SYS_NAND_FTIM3 0x0
109 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
110 #define CONFIG_MTD_NAND_VERIFY_WRITE
113 #ifdef CONFIG_NAND_BOOT
114 #define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10)
117 #if defined(CONFIG_TFABOOT) || \
118 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
125 #ifdef CONFIG_FSL_QIXIS
126 #define QIXIS_BASE 0x7fb00000
127 #define QIXIS_BASE_PHYS QIXIS_BASE
128 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
129 #define QIXIS_LBMAP_SWITCH 6
130 #define QIXIS_LBMAP_MASK 0x0f
131 #define QIXIS_LBMAP_SHIFT 0
132 #define QIXIS_LBMAP_DFLTBANK 0x00
133 #define QIXIS_LBMAP_ALTBANK 0x04
134 #define QIXIS_LBMAP_NAND 0x09
135 #define QIXIS_LBMAP_SD 0x00
136 #define QIXIS_LBMAP_SD_QSPI 0xff
137 #define QIXIS_LBMAP_QSPI 0xff
138 #define QIXIS_RCW_SRC_NAND 0x106
139 #define QIXIS_RCW_SRC_SD 0x040
140 #define QIXIS_RCW_SRC_QSPI 0x045
141 #define QIXIS_RST_CTL_RESET 0x41
142 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
143 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
144 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
146 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
147 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
151 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
152 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
153 CSOR_NOR_NOR_MODE_AVD_NOR | \
157 * QIXIS Timing parameters for IFC GPCM
159 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
160 FTIM0_GPCM_TEADC(0x20) | \
161 FTIM0_GPCM_TEAHC(0x10))
162 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
163 FTIM1_GPCM_TRAD(0x1f))
164 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
165 FTIM2_GPCM_TCH(0x8) | \
166 FTIM2_GPCM_TWP(0xf0))
167 #define CONFIG_SYS_FPGA_FTIM3 0x0
170 #ifdef CONFIG_TFABOOT
171 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
172 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
173 #define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
174 #define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
175 #define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
176 #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
177 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
178 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
179 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
180 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
181 #define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
182 #define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
183 #define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
184 #define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
185 #define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
186 #define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
187 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
188 #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
189 #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
190 #define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
191 #define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
192 #define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
193 #define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
194 #define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
195 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
196 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
197 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
198 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
199 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
200 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
201 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
202 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
204 #ifdef CONFIG_NAND_BOOT
205 #define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
206 #define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
207 #define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
208 #define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
209 #define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
210 #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
211 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
212 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
213 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
214 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
215 #define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
216 #define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
217 #define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
218 #define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
219 #define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
220 #define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
221 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
222 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
223 #define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
224 #define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
225 #define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
226 #define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
227 #define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
228 #define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
229 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
230 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
231 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
232 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
233 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
234 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
235 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
236 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
240 #define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
247 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
248 #define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
249 #define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
250 #define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
254 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
263 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
264 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
265 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
266 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
267 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
268 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
269 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
274 * I2C bus multiplexer
276 #define I2C_MUX_PCA_ADDR_PRI 0x77
277 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
278 #define I2C_RETIMER_ADDR 0x18
279 #define I2C_MUX_CH_DEFAULT 0x8
280 #define I2C_MUX_CH_CH7301 0xC
281 #define I2C_MUX_CH5 0xD
282 #define I2C_MUX_CH7 0xF
284 #define I2C_MUX_CH_VOL_MONITOR 0xa
286 /* Voltage monitor on channel 2*/
287 #define I2C_VOL_MONITOR_ADDR 0x40
288 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
289 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
290 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
292 /* The lowest and highest voltage allowed for LS1043AQDS */
293 #define VDD_MV_MIN 819
294 #define VDD_MV_MAX 1212
297 * Miscellaneous configurable options
304 #include <asm/fsl_secure_boot.h>
306 #endif /* __LS1043AQDS_H__ */