1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
12 unsigned long get_board_sys_clk(void);
13 unsigned long get_board_ddr_clk(void);
16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_LAYERSCAPE_NS_ACCESS
23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
24 /* Physical Memory Map */
25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
27 #define CONFIG_DDR_SPD
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0
31 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
37 #ifdef CONFIG_SYS_DPAA_FMAN
38 #define CONFIG_FMAN_ENET
39 #define CONFIG_PHY_VITESSE
40 #define CONFIG_PHY_REALTEK
41 #define CONFIG_PHYLIB_10G
42 #define RGMII_PHY1_ADDR 0x1
43 #define RGMII_PHY2_ADDR 0x2
44 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
45 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
46 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
47 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
48 /* PHY address on QSGMII riser card on slot 1 */
49 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
50 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
51 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
52 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
53 /* PHY address on QSGMII riser card on slot 2 */
54 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
55 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
56 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
57 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
60 #ifdef CONFIG_RAMBOOT_PBL
61 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
64 #ifdef CONFIG_NAND_BOOT
65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
69 #ifdef CONFIG_SD_BOOT_QSPI
70 #define CONFIG_SYS_FSL_PBL_RCW \
71 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
79 #define CONFIG_LPUART_32B_REG
83 #define CONFIG_SCSI_AHCI_PLAT
86 #define CONFIG_ID_EEPROM
87 #define CONFIG_SYS_I2C_EEPROM_NXID
88 #define CONFIG_SYS_EEPROM_BUS_NUM 0
89 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
90 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
91 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
92 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
94 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
96 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
97 #define CONFIG_SYS_SCSI_MAX_LUN 1
98 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
99 CONFIG_SYS_SCSI_MAX_LUN)
104 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
105 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
106 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
107 CSPR_PORT_SIZE_16 | \
110 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
111 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
113 CSPR_PORT_SIZE_16 | \
116 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
118 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
120 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
121 FTIM0_NOR_TEADC(0x5) | \
122 FTIM0_NOR_TEAHC(0x5))
123 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
124 FTIM1_NOR_TRAD_NOR(0x1a) | \
125 FTIM1_NOR_TSEQRAD_NOR(0x13))
126 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
127 FTIM2_NOR_TCH(0x4) | \
128 FTIM2_NOR_TWPH(0xe) | \
130 #define CONFIG_SYS_NOR_FTIM3 0
132 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
133 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
137 #define CONFIG_SYS_FLASH_EMPTY_INFO
138 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
139 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
141 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
142 #define CONFIG_SYS_WRITE_SWAPPED_DATA
145 * NAND Flash Definitions
147 #define CONFIG_NAND_FSL_IFC
149 #define CONFIG_SYS_NAND_BASE 0x7e800000
150 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
152 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
154 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
158 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
159 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
160 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
161 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
162 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
163 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
164 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
165 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
167 #define CONFIG_SYS_NAND_ONFI_DETECTION
169 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
170 FTIM0_NAND_TWP(0x18) | \
171 FTIM0_NAND_TWCHT(0x7) | \
173 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
174 FTIM1_NAND_TWBE(0x39) | \
175 FTIM1_NAND_TRR(0xe) | \
176 FTIM1_NAND_TRP(0x18))
177 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
178 FTIM2_NAND_TREH(0xa) | \
179 FTIM2_NAND_TWHRE(0x1e))
180 #define CONFIG_SYS_NAND_FTIM3 0x0
182 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
183 #define CONFIG_SYS_MAX_NAND_DEVICE 1
184 #define CONFIG_MTD_NAND_VERIFY_WRITE
186 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
189 #ifdef CONFIG_NAND_BOOT
190 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
191 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
195 #if defined(CONFIG_TFABOOT) || \
196 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
197 #define CONFIG_QIXIS_I2C_ACCESS
198 #define CONFIG_SYS_I2C_EARLY_INIT
204 #define CONFIG_FSL_QIXIS
206 #ifdef CONFIG_FSL_QIXIS
207 #define QIXIS_BASE 0x7fb00000
208 #define QIXIS_BASE_PHYS QIXIS_BASE
209 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
210 #define QIXIS_LBMAP_SWITCH 6
211 #define QIXIS_LBMAP_MASK 0x0f
212 #define QIXIS_LBMAP_SHIFT 0
213 #define QIXIS_LBMAP_DFLTBANK 0x00
214 #define QIXIS_LBMAP_ALTBANK 0x04
215 #define QIXIS_LBMAP_NAND 0x09
216 #define QIXIS_LBMAP_SD 0x00
217 #define QIXIS_LBMAP_SD_QSPI 0xff
218 #define QIXIS_LBMAP_QSPI 0xff
219 #define QIXIS_RCW_SRC_NAND 0x106
220 #define QIXIS_RCW_SRC_SD 0x040
221 #define QIXIS_RCW_SRC_QSPI 0x045
222 #define QIXIS_RST_CTL_RESET 0x41
223 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
224 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
225 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
227 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
228 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
232 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
233 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
234 CSOR_NOR_NOR_MODE_AVD_NOR | \
238 * QIXIS Timing parameters for IFC GPCM
240 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
241 FTIM0_GPCM_TEADC(0x20) | \
242 FTIM0_GPCM_TEAHC(0x10))
243 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
244 FTIM1_GPCM_TRAD(0x1f))
245 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
246 FTIM2_GPCM_TCH(0x8) | \
247 FTIM2_GPCM_TWP(0xf0))
248 #define CONFIG_SYS_FPGA_FTIM3 0x0
251 #ifdef CONFIG_TFABOOT
252 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
253 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
254 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
261 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
262 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
263 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
264 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
265 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
266 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
267 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
268 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
269 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
270 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
271 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
272 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
273 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
274 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
275 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
276 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
277 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
278 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
279 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
280 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
281 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
282 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
283 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
285 #ifdef CONFIG_NAND_BOOT
286 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
294 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
295 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
296 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
297 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
298 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
299 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
300 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
301 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
302 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
303 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
304 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
305 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
306 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
307 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
308 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
309 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
310 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
311 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
312 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
313 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
314 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
315 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
316 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
317 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
319 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
320 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
321 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
327 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
328 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
329 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
330 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
331 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
332 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
333 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
334 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
335 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
336 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
337 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
338 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
339 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
340 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
341 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
342 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
343 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
344 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
345 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
346 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
347 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
348 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
349 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
350 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
355 * I2C bus multiplexer
357 #define I2C_MUX_PCA_ADDR_PRI 0x77
358 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
359 #define I2C_RETIMER_ADDR 0x18
360 #define I2C_MUX_CH_DEFAULT 0x8
361 #define I2C_MUX_CH_CH7301 0xC
362 #define I2C_MUX_CH5 0xD
363 #define I2C_MUX_CH7 0xF
365 #define I2C_MUX_CH_VOL_MONITOR 0xa
367 /* Voltage monitor on channel 2*/
368 #define I2C_VOL_MONITOR_ADDR 0x40
369 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
370 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
371 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
373 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
374 #ifndef CONFIG_SPL_BUILD
377 #define CONFIG_VOL_MONITOR_IR36021_SET
378 #define CONFIG_VOL_MONITOR_INA220
379 /* The lowest and highest voltage allowed for LS1043AQDS */
380 #define VDD_MV_MIN 819
381 #define VDD_MV_MAX 1212
384 #if defined(CONFIG_TFABOOT) || \
385 (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
386 #define CONFIG_FSL_QSPI
387 #ifdef CONFIG_FSL_QSPI
388 #define CONFIG_SPI_FLASH_SPANSION
389 #define FSL_QSPI_FLASH_SIZE (1 << 24)
390 #define FSL_QSPI_FLASH_NUM 2
395 * Miscellaneous configurable options
398 #define CONFIG_SYS_MEMTEST_START 0x80000000
399 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
401 #define CONFIG_SYS_HZ 1000
403 #define CONFIG_SYS_INIT_SP_OFFSET \
404 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
406 #ifdef CONFIG_SPL_BUILD
407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
415 #define CONFIG_ENV_OVERWRITE
417 #ifdef CONFIG_TFABOOT
418 #define CONFIG_SYS_MMC_ENV_DEV 0
420 #define CONFIG_ENV_SIZE 0x2000
421 #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
422 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000)
423 #define CONFIG_ENV_SECT_SIZE 0x20000
425 #ifdef CONFIG_NAND_BOOT
426 #define CONFIG_ENV_SIZE 0x2000
427 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
428 #elif defined(CONFIG_SD_BOOT)
429 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
430 #define CONFIG_SYS_MMC_ENV_DEV 0
431 #define CONFIG_ENV_SIZE 0x2000
432 #elif defined(CONFIG_QSPI_BOOT)
433 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
434 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
435 #define CONFIG_ENV_SECT_SIZE 0x10000
437 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
438 #define CONFIG_ENV_SECT_SIZE 0x20000
439 #define CONFIG_ENV_SIZE 0x20000
443 #define CONFIG_CMDLINE_TAG
445 #include <asm/fsl_secure_boot.h>
447 #endif /* __LS1043AQDS_H__ */