1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 /* Physical Memory Map */
16 #define SPD_EEPROM_ADDRESS 0x51
17 #define CONFIG_SYS_SPD_BUS_NUM 0
20 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
23 #ifdef CONFIG_SYS_DPAA_FMAN
24 #define RGMII_PHY1_ADDR 0x1
25 #define RGMII_PHY2_ADDR 0x2
26 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
27 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
28 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
29 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
30 /* PHY address on QSGMII riser card on slot 1 */
31 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
32 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
33 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
34 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
35 /* PHY address on QSGMII riser card on slot 2 */
36 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
37 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
38 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
39 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
44 #define CONFIG_LPUART_32B_REG
50 #define CONFIG_SYS_I2C_EEPROM_NXID
51 #define CONFIG_SYS_EEPROM_BUS_NUM 0
53 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
58 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
59 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
60 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
64 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
65 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
70 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
72 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
74 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
75 FTIM0_NOR_TEADC(0x5) | \
77 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
78 FTIM1_NOR_TRAD_NOR(0x1a) | \
79 FTIM1_NOR_TSEQRAD_NOR(0x13))
80 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
81 FTIM2_NOR_TCH(0x4) | \
82 FTIM2_NOR_TWPH(0xe) | \
84 #define CONFIG_SYS_NOR_FTIM3 0
86 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
87 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
88 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
90 #define CONFIG_SYS_FLASH_EMPTY_INFO
91 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
92 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
94 #define CONFIG_SYS_WRITE_SWAPPED_DATA
97 * NAND Flash Definitions
100 #define CONFIG_SYS_NAND_BASE 0x7e800000
101 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
103 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
105 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
109 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
110 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
111 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
112 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
113 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
114 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
115 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
116 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
118 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
119 FTIM0_NAND_TWP(0x18) | \
120 FTIM0_NAND_TWCHT(0x7) | \
122 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
123 FTIM1_NAND_TWBE(0x39) | \
124 FTIM1_NAND_TRR(0xe) | \
125 FTIM1_NAND_TRP(0x18))
126 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
127 FTIM2_NAND_TREH(0xa) | \
128 FTIM2_NAND_TWHRE(0x1e))
129 #define CONFIG_SYS_NAND_FTIM3 0x0
131 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1
133 #define CONFIG_MTD_NAND_VERIFY_WRITE
136 #ifdef CONFIG_NAND_BOOT
137 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
138 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
141 #if defined(CONFIG_TFABOOT) || \
142 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
143 #define CONFIG_QIXIS_I2C_ACCESS
149 #define CONFIG_FSL_QIXIS
151 #ifdef CONFIG_FSL_QIXIS
152 #define QIXIS_BASE 0x7fb00000
153 #define QIXIS_BASE_PHYS QIXIS_BASE
154 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
155 #define QIXIS_LBMAP_SWITCH 6
156 #define QIXIS_LBMAP_MASK 0x0f
157 #define QIXIS_LBMAP_SHIFT 0
158 #define QIXIS_LBMAP_DFLTBANK 0x00
159 #define QIXIS_LBMAP_ALTBANK 0x04
160 #define QIXIS_LBMAP_NAND 0x09
161 #define QIXIS_LBMAP_SD 0x00
162 #define QIXIS_LBMAP_SD_QSPI 0xff
163 #define QIXIS_LBMAP_QSPI 0xff
164 #define QIXIS_RCW_SRC_NAND 0x106
165 #define QIXIS_RCW_SRC_SD 0x040
166 #define QIXIS_RCW_SRC_QSPI 0x045
167 #define QIXIS_RST_CTL_RESET 0x41
168 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
169 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
170 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
172 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
173 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
177 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
178 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
179 CSOR_NOR_NOR_MODE_AVD_NOR | \
183 * QIXIS Timing parameters for IFC GPCM
185 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
186 FTIM0_GPCM_TEADC(0x20) | \
187 FTIM0_GPCM_TEAHC(0x10))
188 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
189 FTIM1_GPCM_TRAD(0x1f))
190 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
191 FTIM2_GPCM_TCH(0x8) | \
192 FTIM2_GPCM_TWP(0xf0))
193 #define CONFIG_SYS_FPGA_FTIM3 0x0
196 #ifdef CONFIG_TFABOOT
197 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
198 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
199 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
200 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
201 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
202 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
203 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
204 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
205 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
206 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
207 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
208 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
209 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
210 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
211 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
212 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
213 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
214 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
215 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
216 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
217 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
218 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
219 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
220 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
221 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
222 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
223 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
224 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
225 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
226 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
227 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
228 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
230 #ifdef CONFIG_NAND_BOOT
231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
233 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
234 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
235 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
236 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
237 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
238 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
239 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
240 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
241 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
248 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
249 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
250 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
251 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
252 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
253 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
254 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
255 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
256 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
257 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
258 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
259 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
260 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
261 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
262 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
281 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
282 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
283 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
284 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
285 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
286 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
287 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
288 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
289 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
290 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
291 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
292 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
293 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
294 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
295 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
300 * I2C bus multiplexer
302 #define I2C_MUX_PCA_ADDR_PRI 0x77
303 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
304 #define I2C_RETIMER_ADDR 0x18
305 #define I2C_MUX_CH_DEFAULT 0x8
306 #define I2C_MUX_CH_CH7301 0xC
307 #define I2C_MUX_CH5 0xD
308 #define I2C_MUX_CH7 0xF
310 #define I2C_MUX_CH_VOL_MONITOR 0xa
312 /* Voltage monitor on channel 2*/
313 #define I2C_VOL_MONITOR_ADDR 0x40
314 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
315 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
316 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
318 /* The lowest and highest voltage allowed for LS1043AQDS */
319 #define VDD_MV_MIN 819
320 #define VDD_MV_MAX 1212
323 * Miscellaneous configurable options
326 #define CONFIG_SYS_INIT_SP_OFFSET \
327 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
329 #ifdef CONFIG_SPL_BUILD
330 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
332 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
339 #include <asm/fsl_secure_boot.h>
341 #endif /* __LS1043AQDS_H__ */