1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 /* Physical Memory Map */
15 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
17 #define SPD_EEPROM_ADDRESS 0x51
18 #define CONFIG_SYS_SPD_BUS_NUM 0
21 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
24 #ifdef CONFIG_SYS_DPAA_FMAN
25 #define RGMII_PHY1_ADDR 0x1
26 #define RGMII_PHY2_ADDR 0x2
27 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
28 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
29 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
30 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
31 /* PHY address on QSGMII riser card on slot 1 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
36 /* PHY address on QSGMII riser card on slot 2 */
37 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
38 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
39 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
40 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
45 #define CONFIG_LPUART_32B_REG
49 #define CONFIG_SCSI_AHCI_PLAT
52 #define CONFIG_SYS_I2C_EEPROM_NXID
53 #define CONFIG_SYS_EEPROM_BUS_NUM 0
55 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
57 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
58 #define CONFIG_SYS_SCSI_MAX_LUN 1
59 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
60 CONFIG_SYS_SCSI_MAX_LUN)
65 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
66 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
67 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
71 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
72 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
77 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
79 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
81 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
82 FTIM0_NOR_TEADC(0x5) | \
84 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
85 FTIM1_NOR_TRAD_NOR(0x1a) | \
86 FTIM1_NOR_TSEQRAD_NOR(0x13))
87 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
88 FTIM2_NOR_TCH(0x4) | \
89 FTIM2_NOR_TWPH(0xe) | \
91 #define CONFIG_SYS_NOR_FTIM3 0
93 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98 #define CONFIG_SYS_FLASH_EMPTY_INFO
99 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
100 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
102 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
103 #define CONFIG_SYS_WRITE_SWAPPED_DATA
106 * NAND Flash Definitions
109 #define CONFIG_SYS_NAND_BASE 0x7e800000
110 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
112 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
114 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
118 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
119 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
120 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
121 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
122 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
123 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
124 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
125 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
127 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
128 FTIM0_NAND_TWP(0x18) | \
129 FTIM0_NAND_TWCHT(0x7) | \
131 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
132 FTIM1_NAND_TWBE(0x39) | \
133 FTIM1_NAND_TRR(0xe) | \
134 FTIM1_NAND_TRP(0x18))
135 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
136 FTIM2_NAND_TREH(0xa) | \
137 FTIM2_NAND_TWHRE(0x1e))
138 #define CONFIG_SYS_NAND_FTIM3 0x0
140 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1
142 #define CONFIG_MTD_NAND_VERIFY_WRITE
145 #ifdef CONFIG_NAND_BOOT
146 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
147 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
150 #if defined(CONFIG_TFABOOT) || \
151 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
152 #define CONFIG_QIXIS_I2C_ACCESS
158 #define CONFIG_FSL_QIXIS
160 #ifdef CONFIG_FSL_QIXIS
161 #define QIXIS_BASE 0x7fb00000
162 #define QIXIS_BASE_PHYS QIXIS_BASE
163 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
164 #define QIXIS_LBMAP_SWITCH 6
165 #define QIXIS_LBMAP_MASK 0x0f
166 #define QIXIS_LBMAP_SHIFT 0
167 #define QIXIS_LBMAP_DFLTBANK 0x00
168 #define QIXIS_LBMAP_ALTBANK 0x04
169 #define QIXIS_LBMAP_NAND 0x09
170 #define QIXIS_LBMAP_SD 0x00
171 #define QIXIS_LBMAP_SD_QSPI 0xff
172 #define QIXIS_LBMAP_QSPI 0xff
173 #define QIXIS_RCW_SRC_NAND 0x106
174 #define QIXIS_RCW_SRC_SD 0x040
175 #define QIXIS_RCW_SRC_QSPI 0x045
176 #define QIXIS_RST_CTL_RESET 0x41
177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
181 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
182 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
186 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
187 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
188 CSOR_NOR_NOR_MODE_AVD_NOR | \
192 * QIXIS Timing parameters for IFC GPCM
194 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
195 FTIM0_GPCM_TEADC(0x20) | \
196 FTIM0_GPCM_TEAHC(0x10))
197 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
198 FTIM1_GPCM_TRAD(0x1f))
199 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
200 FTIM2_GPCM_TCH(0x8) | \
201 FTIM2_GPCM_TWP(0xf0))
202 #define CONFIG_SYS_FPGA_FTIM3 0x0
205 #ifdef CONFIG_TFABOOT
206 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
207 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
208 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
209 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
210 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
211 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
212 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
213 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
214 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
215 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
216 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
217 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
218 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
219 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
220 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
221 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
222 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
223 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
230 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
231 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
232 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
233 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
234 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
235 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
236 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
237 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
239 #ifdef CONFIG_NAND_BOOT
240 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
241 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
242 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
243 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
244 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
245 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
246 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
247 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
248 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
249 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
251 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
252 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
253 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
254 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
255 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
256 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
257 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
258 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
259 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
260 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
261 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
262 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
263 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
264 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
265 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
266 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
267 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
268 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
269 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
270 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
271 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
273 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
281 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
282 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
283 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
284 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
285 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
286 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
287 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
288 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
289 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
290 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
291 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
292 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
293 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
294 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
295 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
296 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
297 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
298 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
299 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
300 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
301 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
302 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
303 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
304 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
309 * I2C bus multiplexer
311 #define I2C_MUX_PCA_ADDR_PRI 0x77
312 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
313 #define I2C_RETIMER_ADDR 0x18
314 #define I2C_MUX_CH_DEFAULT 0x8
315 #define I2C_MUX_CH_CH7301 0xC
316 #define I2C_MUX_CH5 0xD
317 #define I2C_MUX_CH7 0xF
319 #define I2C_MUX_CH_VOL_MONITOR 0xa
321 /* Voltage monitor on channel 2*/
322 #define I2C_VOL_MONITOR_ADDR 0x40
323 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
324 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
325 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
327 /* The lowest and highest voltage allowed for LS1043AQDS */
328 #define VDD_MV_MIN 819
329 #define VDD_MV_MAX 1212
332 * Miscellaneous configurable options
335 #define CONFIG_SYS_INIT_SP_OFFSET \
336 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
338 #ifdef CONFIG_SPL_BUILD
339 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
341 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
348 #include <asm/fsl_secure_boot.h>
350 #endif /* __LS1043AQDS_H__ */