1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 1 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
41 #define CONFIG_SYS_I2C_EEPROM_NXID
42 #define CONFIG_SYS_EEPROM_BUS_NUM 0
44 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
49 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
50 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
51 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
55 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
56 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
61 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
63 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
65 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
66 FTIM0_NOR_TEADC(0x5) | \
68 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
69 FTIM1_NOR_TRAD_NOR(0x1a) | \
70 FTIM1_NOR_TSEQRAD_NOR(0x13))
71 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
72 FTIM2_NOR_TCH(0x4) | \
73 FTIM2_NOR_TWPH(0xe) | \
75 #define CONFIG_SYS_NOR_FTIM3 0
77 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
78 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
79 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
81 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
82 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
84 #define CONFIG_SYS_WRITE_SWAPPED_DATA
87 * NAND Flash Definitions
90 #define CONFIG_SYS_NAND_BASE 0x7e800000
91 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
93 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
95 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
99 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
100 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
101 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
102 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
103 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
104 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
105 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
106 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
108 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
109 FTIM0_NAND_TWP(0x18) | \
110 FTIM0_NAND_TWCHT(0x7) | \
112 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
113 FTIM1_NAND_TWBE(0x39) | \
114 FTIM1_NAND_TRR(0xe) | \
115 FTIM1_NAND_TRP(0x18))
116 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
117 FTIM2_NAND_TREH(0xa) | \
118 FTIM2_NAND_TWHRE(0x1e))
119 #define CONFIG_SYS_NAND_FTIM3 0x0
121 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
122 #define CONFIG_SYS_MAX_NAND_DEVICE 1
123 #define CONFIG_MTD_NAND_VERIFY_WRITE
126 #ifdef CONFIG_NAND_BOOT
127 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
130 #if defined(CONFIG_TFABOOT) || \
131 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
138 #ifdef CONFIG_FSL_QIXIS
139 #define QIXIS_BASE 0x7fb00000
140 #define QIXIS_BASE_PHYS QIXIS_BASE
141 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
142 #define QIXIS_LBMAP_SWITCH 6
143 #define QIXIS_LBMAP_MASK 0x0f
144 #define QIXIS_LBMAP_SHIFT 0
145 #define QIXIS_LBMAP_DFLTBANK 0x00
146 #define QIXIS_LBMAP_ALTBANK 0x04
147 #define QIXIS_LBMAP_NAND 0x09
148 #define QIXIS_LBMAP_SD 0x00
149 #define QIXIS_LBMAP_SD_QSPI 0xff
150 #define QIXIS_LBMAP_QSPI 0xff
151 #define QIXIS_RCW_SRC_NAND 0x106
152 #define QIXIS_RCW_SRC_SD 0x040
153 #define QIXIS_RCW_SRC_QSPI 0x045
154 #define QIXIS_RST_CTL_RESET 0x41
155 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
156 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
157 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
159 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
160 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
164 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
165 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
166 CSOR_NOR_NOR_MODE_AVD_NOR | \
170 * QIXIS Timing parameters for IFC GPCM
172 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
173 FTIM0_GPCM_TEADC(0x20) | \
174 FTIM0_GPCM_TEAHC(0x10))
175 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
176 FTIM1_GPCM_TRAD(0x1f))
177 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
178 FTIM2_GPCM_TCH(0x8) | \
179 FTIM2_GPCM_TWP(0xf0))
180 #define CONFIG_SYS_FPGA_FTIM3 0x0
183 #ifdef CONFIG_TFABOOT
184 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
185 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
186 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
187 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
188 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
189 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
190 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
191 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
192 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
193 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
194 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
195 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
196 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
197 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
198 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
199 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
200 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
201 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
202 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
203 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
204 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
205 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
206 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
207 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
208 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
209 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
210 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
211 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
212 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
213 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
214 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
215 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
217 #ifdef CONFIG_NAND_BOOT
218 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
226 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
227 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
228 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
229 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
230 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
231 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
232 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
233 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
234 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
235 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
236 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
237 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
238 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
239 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
240 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
241 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
242 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
243 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
244 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
245 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
246 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
247 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
248 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
249 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
251 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
252 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
253 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
254 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
255 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
256 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
257 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
258 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
259 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
260 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
261 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
262 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
263 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
264 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
265 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
266 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
267 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
268 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
269 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
270 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
271 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
272 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
273 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
274 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
275 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
276 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
277 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
278 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
279 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
280 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
281 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
282 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
287 * I2C bus multiplexer
289 #define I2C_MUX_PCA_ADDR_PRI 0x77
290 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
291 #define I2C_RETIMER_ADDR 0x18
292 #define I2C_MUX_CH_DEFAULT 0x8
293 #define I2C_MUX_CH_CH7301 0xC
294 #define I2C_MUX_CH5 0xD
295 #define I2C_MUX_CH7 0xF
297 #define I2C_MUX_CH_VOL_MONITOR 0xa
299 /* Voltage monitor on channel 2*/
300 #define I2C_VOL_MONITOR_ADDR 0x40
301 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
302 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
303 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
305 /* The lowest and highest voltage allowed for LS1043AQDS */
306 #define VDD_MV_MIN 819
307 #define VDD_MV_MAX 1212
310 * Miscellaneous configurable options
317 #include <asm/fsl_secure_boot.h>
319 #endif /* __LS1043AQDS_H__ */