1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 #define CONFIG_LAYERSCAPE_NS_ACCESS
13 /* Physical Memory Map */
15 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_SYS_SPD_BUS_NUM 0
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
22 #ifdef CONFIG_SYS_DPAA_FMAN
23 #define RGMII_PHY1_ADDR 0x1
24 #define RGMII_PHY2_ADDR 0x2
25 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
26 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
27 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
28 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
29 /* PHY address on QSGMII riser card on slot 1 */
30 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
31 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
32 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
33 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
34 /* PHY address on QSGMII riser card on slot 2 */
35 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
36 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
37 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
38 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
44 #define CONFIG_SYS_I2C_EEPROM_NXID
45 #define CONFIG_SYS_EEPROM_BUS_NUM 0
47 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
53 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
54 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
58 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
59 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
66 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
68 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
69 FTIM0_NOR_TEADC(0x5) | \
71 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
72 FTIM1_NOR_TRAD_NOR(0x1a) | \
73 FTIM1_NOR_TSEQRAD_NOR(0x13))
74 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
75 FTIM2_NOR_TCH(0x4) | \
76 FTIM2_NOR_TWPH(0xe) | \
78 #define CONFIG_SYS_NOR_FTIM3 0
80 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
81 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
82 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
84 #define CONFIG_SYS_FLASH_EMPTY_INFO
85 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
86 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
88 #define CONFIG_SYS_WRITE_SWAPPED_DATA
91 * NAND Flash Definitions
94 #define CONFIG_SYS_NAND_BASE 0x7e800000
95 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
97 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
99 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
103 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
104 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
106 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
107 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
108 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
109 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
110 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
112 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
113 FTIM0_NAND_TWP(0x18) | \
114 FTIM0_NAND_TWCHT(0x7) | \
116 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
117 FTIM1_NAND_TWBE(0x39) | \
118 FTIM1_NAND_TRR(0xe) | \
119 FTIM1_NAND_TRP(0x18))
120 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
121 FTIM2_NAND_TREH(0xa) | \
122 FTIM2_NAND_TWHRE(0x1e))
123 #define CONFIG_SYS_NAND_FTIM3 0x0
125 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
126 #define CONFIG_SYS_MAX_NAND_DEVICE 1
127 #define CONFIG_MTD_NAND_VERIFY_WRITE
130 #ifdef CONFIG_NAND_BOOT
131 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
134 #if defined(CONFIG_TFABOOT) || \
135 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
142 #ifdef CONFIG_FSL_QIXIS
143 #define QIXIS_BASE 0x7fb00000
144 #define QIXIS_BASE_PHYS QIXIS_BASE
145 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
146 #define QIXIS_LBMAP_SWITCH 6
147 #define QIXIS_LBMAP_MASK 0x0f
148 #define QIXIS_LBMAP_SHIFT 0
149 #define QIXIS_LBMAP_DFLTBANK 0x00
150 #define QIXIS_LBMAP_ALTBANK 0x04
151 #define QIXIS_LBMAP_NAND 0x09
152 #define QIXIS_LBMAP_SD 0x00
153 #define QIXIS_LBMAP_SD_QSPI 0xff
154 #define QIXIS_LBMAP_QSPI 0xff
155 #define QIXIS_RCW_SRC_NAND 0x106
156 #define QIXIS_RCW_SRC_SD 0x040
157 #define QIXIS_RCW_SRC_QSPI 0x045
158 #define QIXIS_RST_CTL_RESET 0x41
159 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
160 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
161 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
163 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
164 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
168 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
169 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
170 CSOR_NOR_NOR_MODE_AVD_NOR | \
174 * QIXIS Timing parameters for IFC GPCM
176 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
177 FTIM0_GPCM_TEADC(0x20) | \
178 FTIM0_GPCM_TEAHC(0x10))
179 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
180 FTIM1_GPCM_TRAD(0x1f))
181 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
182 FTIM2_GPCM_TCH(0x8) | \
183 FTIM2_GPCM_TWP(0xf0))
184 #define CONFIG_SYS_FPGA_FTIM3 0x0
187 #ifdef CONFIG_TFABOOT
188 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
189 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
190 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
196 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
197 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
198 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
205 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
206 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
207 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
208 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
209 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
210 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
211 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
212 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
213 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
214 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
215 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
216 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
217 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
218 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
219 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
221 #ifdef CONFIG_NAND_BOOT
222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
230 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
231 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
232 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
239 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
240 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
247 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
248 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
249 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
250 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
251 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
252 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
253 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
255 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
256 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
257 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
258 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
263 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
264 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
265 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
266 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
267 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
268 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
269 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
270 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
271 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
272 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
273 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
274 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
275 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
276 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
277 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
278 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
279 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
280 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
281 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
282 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
283 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
284 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
285 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
286 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
291 * I2C bus multiplexer
293 #define I2C_MUX_PCA_ADDR_PRI 0x77
294 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
295 #define I2C_RETIMER_ADDR 0x18
296 #define I2C_MUX_CH_DEFAULT 0x8
297 #define I2C_MUX_CH_CH7301 0xC
298 #define I2C_MUX_CH5 0xD
299 #define I2C_MUX_CH7 0xF
301 #define I2C_MUX_CH_VOL_MONITOR 0xa
303 /* Voltage monitor on channel 2*/
304 #define I2C_VOL_MONITOR_ADDR 0x40
305 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
306 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
307 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
309 /* The lowest and highest voltage allowed for LS1043AQDS */
310 #define VDD_MV_MIN 819
311 #define VDD_MV_MAX 1212
314 * Miscellaneous configurable options
321 #include <asm/fsl_secure_boot.h>
323 #endif /* __LS1043AQDS_H__ */