1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 1 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
41 #define CONFIG_SYS_I2C_EEPROM_NXID
42 #define CONFIG_SYS_EEPROM_BUS_NUM 0
44 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
49 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
50 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
51 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
55 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
56 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
61 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
63 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
65 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
66 FTIM0_NOR_TEADC(0x5) | \
68 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
69 FTIM1_NOR_TRAD_NOR(0x1a) | \
70 FTIM1_NOR_TSEQRAD_NOR(0x13))
71 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
72 FTIM2_NOR_TCH(0x4) | \
73 FTIM2_NOR_TWPH(0xe) | \
75 #define CONFIG_SYS_NOR_FTIM3 0
77 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
78 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
80 #define CONFIG_SYS_WRITE_SWAPPED_DATA
83 * NAND Flash Definitions
86 #define CONFIG_SYS_NAND_BASE 0x7e800000
87 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
89 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
91 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
95 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
96 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
97 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
98 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
99 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
100 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
101 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
102 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
104 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
105 FTIM0_NAND_TWP(0x18) | \
106 FTIM0_NAND_TWCHT(0x7) | \
108 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
109 FTIM1_NAND_TWBE(0x39) | \
110 FTIM1_NAND_TRR(0xe) | \
111 FTIM1_NAND_TRP(0x18))
112 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
113 FTIM2_NAND_TREH(0xa) | \
114 FTIM2_NAND_TWHRE(0x1e))
115 #define CONFIG_SYS_NAND_FTIM3 0x0
117 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 #define CONFIG_MTD_NAND_VERIFY_WRITE
122 #ifdef CONFIG_NAND_BOOT
123 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
126 #if defined(CONFIG_TFABOOT) || \
127 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
134 #ifdef CONFIG_FSL_QIXIS
135 #define QIXIS_BASE 0x7fb00000
136 #define QIXIS_BASE_PHYS QIXIS_BASE
137 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
138 #define QIXIS_LBMAP_SWITCH 6
139 #define QIXIS_LBMAP_MASK 0x0f
140 #define QIXIS_LBMAP_SHIFT 0
141 #define QIXIS_LBMAP_DFLTBANK 0x00
142 #define QIXIS_LBMAP_ALTBANK 0x04
143 #define QIXIS_LBMAP_NAND 0x09
144 #define QIXIS_LBMAP_SD 0x00
145 #define QIXIS_LBMAP_SD_QSPI 0xff
146 #define QIXIS_LBMAP_QSPI 0xff
147 #define QIXIS_RCW_SRC_NAND 0x106
148 #define QIXIS_RCW_SRC_SD 0x040
149 #define QIXIS_RCW_SRC_QSPI 0x045
150 #define QIXIS_RST_CTL_RESET 0x41
151 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
152 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
153 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
155 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
156 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
160 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
161 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
162 CSOR_NOR_NOR_MODE_AVD_NOR | \
166 * QIXIS Timing parameters for IFC GPCM
168 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
169 FTIM0_GPCM_TEADC(0x20) | \
170 FTIM0_GPCM_TEAHC(0x10))
171 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
172 FTIM1_GPCM_TRAD(0x1f))
173 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
174 FTIM2_GPCM_TCH(0x8) | \
175 FTIM2_GPCM_TWP(0xf0))
176 #define CONFIG_SYS_FPGA_FTIM3 0x0
179 #ifdef CONFIG_TFABOOT
180 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
181 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
182 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
183 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
184 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
185 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
186 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
187 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
188 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
189 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
190 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
196 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
197 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
198 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
199 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
200 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
201 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
202 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
203 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
204 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
205 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
206 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
207 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
208 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
209 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
210 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
211 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
213 #ifdef CONFIG_NAND_BOOT
214 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
215 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
216 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
217 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
218 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
219 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
220 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
221 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
222 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
223 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
224 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
225 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
226 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
227 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
228 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
229 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
230 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
231 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
232 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
239 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
240 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
241 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
242 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
243 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
244 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
245 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
247 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
255 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
258 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
259 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
260 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
261 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
262 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
263 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
264 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
265 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
266 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
267 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
268 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
269 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
270 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
271 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
272 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
273 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
274 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
275 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
276 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
277 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
278 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
283 * I2C bus multiplexer
285 #define I2C_MUX_PCA_ADDR_PRI 0x77
286 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
287 #define I2C_RETIMER_ADDR 0x18
288 #define I2C_MUX_CH_DEFAULT 0x8
289 #define I2C_MUX_CH_CH7301 0xC
290 #define I2C_MUX_CH5 0xD
291 #define I2C_MUX_CH7 0xF
293 #define I2C_MUX_CH_VOL_MONITOR 0xa
295 /* Voltage monitor on channel 2*/
296 #define I2C_VOL_MONITOR_ADDR 0x40
297 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
298 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
299 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
301 /* The lowest and highest voltage allowed for LS1043AQDS */
302 #define VDD_MV_MIN 819
303 #define VDD_MV_MAX 1212
306 * Miscellaneous configurable options
313 #include <asm/fsl_secure_boot.h>
315 #endif /* __LS1043AQDS_H__ */