1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 1 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
41 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
42 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
43 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
47 #define CFG_SYS_NOR1_CSPR_EXT (0x0)
48 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
53 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
55 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
57 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
58 FTIM0_NOR_TEADC(0x5) | \
60 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
61 FTIM1_NOR_TRAD_NOR(0x1a) | \
62 FTIM1_NOR_TSEQRAD_NOR(0x13))
63 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
64 FTIM2_NOR_TCH(0x4) | \
65 FTIM2_NOR_TWPH(0xe) | \
67 #define CFG_SYS_NOR_FTIM3 0
69 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
70 CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
72 #define CFG_SYS_WRITE_SWAPPED_DATA
75 * NAND Flash Definitions
78 #define CFG_SYS_NAND_BASE 0x7e800000
79 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
81 #define CFG_SYS_NAND_CSPR_EXT (0x0)
83 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
87 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
88 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
89 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
90 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
91 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
92 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
93 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
94 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
96 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
97 FTIM0_NAND_TWP(0x18) | \
98 FTIM0_NAND_TWCHT(0x7) | \
100 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
101 FTIM1_NAND_TWBE(0x39) | \
102 FTIM1_NAND_TRR(0xe) | \
103 FTIM1_NAND_TRP(0x18))
104 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
105 FTIM2_NAND_TREH(0xa) | \
106 FTIM2_NAND_TWHRE(0x1e))
107 #define CFG_SYS_NAND_FTIM3 0x0
109 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
112 #ifdef CONFIG_NAND_BOOT
113 #define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10)
116 #if defined(CONFIG_TFABOOT) || \
117 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
124 #ifdef CONFIG_FSL_QIXIS
125 #define QIXIS_BASE 0x7fb00000
126 #define QIXIS_BASE_PHYS QIXIS_BASE
127 #define CFG_SYS_I2C_FPGA_ADDR 0x66
128 #define QIXIS_LBMAP_SWITCH 6
129 #define QIXIS_LBMAP_MASK 0x0f
130 #define QIXIS_LBMAP_SHIFT 0
131 #define QIXIS_LBMAP_DFLTBANK 0x00
132 #define QIXIS_LBMAP_ALTBANK 0x04
133 #define QIXIS_LBMAP_NAND 0x09
134 #define QIXIS_LBMAP_SD 0x00
135 #define QIXIS_LBMAP_SD_QSPI 0xff
136 #define QIXIS_LBMAP_QSPI 0xff
137 #define QIXIS_RCW_SRC_NAND 0x106
138 #define QIXIS_RCW_SRC_SD 0x040
139 #define QIXIS_RCW_SRC_QSPI 0x045
140 #define QIXIS_RST_CTL_RESET 0x41
141 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
142 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
143 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
145 #define CFG_SYS_FPGA_CSPR_EXT (0x0)
146 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
150 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
151 #define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
152 CSOR_NOR_NOR_MODE_AVD_NOR | \
156 * QIXIS Timing parameters for IFC GPCM
158 #define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
159 FTIM0_GPCM_TEADC(0x20) | \
160 FTIM0_GPCM_TEAHC(0x10))
161 #define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
162 FTIM1_GPCM_TRAD(0x1f))
163 #define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
164 FTIM2_GPCM_TCH(0x8) | \
165 FTIM2_GPCM_TWP(0xf0))
166 #define CFG_SYS_FPGA_FTIM3 0x0
169 #ifdef CONFIG_TFABOOT
170 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
171 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
172 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
173 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
174 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
175 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
176 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
177 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
178 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
179 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
180 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
181 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
182 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
183 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
184 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
185 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
186 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
187 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
188 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
189 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
190 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
191 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
192 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
193 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
194 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
195 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
196 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
197 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
198 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
199 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
200 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
201 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
203 #ifdef CONFIG_NAND_BOOT
204 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
205 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
206 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
207 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
208 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
209 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
210 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
211 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
212 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
213 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
214 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
215 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
216 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
217 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
218 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
219 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
220 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
221 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
222 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
223 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
224 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
225 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
226 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
227 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
228 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
229 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
230 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
231 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
232 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
233 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
234 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
235 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
237 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
238 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
239 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
240 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
241 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
242 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
243 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
244 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
245 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
246 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
247 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
248 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
249 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
250 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
251 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
252 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
253 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
254 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
255 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
256 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
257 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
258 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
259 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
260 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
261 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
262 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
263 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
264 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
265 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
266 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
267 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
268 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
273 * I2C bus multiplexer
275 #define I2C_MUX_PCA_ADDR_PRI 0x77
276 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
277 #define I2C_RETIMER_ADDR 0x18
278 #define I2C_MUX_CH_DEFAULT 0x8
279 #define I2C_MUX_CH_CH7301 0xC
280 #define I2C_MUX_CH5 0xD
281 #define I2C_MUX_CH7 0xF
283 #define I2C_MUX_CH_VOL_MONITOR 0xa
285 /* Voltage monitor on channel 2*/
286 #define I2C_VOL_MONITOR_ADDR 0x40
287 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
288 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
289 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
291 /* The lowest and highest voltage allowed for LS1043AQDS */
292 #define VDD_MV_MIN 819
293 #define VDD_MV_MAX 1212
296 * Miscellaneous configurable options
303 #include <asm/fsl_secure_boot.h>
305 #endif /* __LS1043AQDS_H__ */