2 * Copyright (C) 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
29 #define CONFIG_REMAKE_ELF
30 #define CONFIG_FSL_LAYERSCAPE
34 #include <asm/arch/stream_id_lsch2.h>
35 #include <asm/arch/config.h>
37 /* Link Definitions */
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
40 #define CONFIG_SKIP_LOWLEVEL_INIT
42 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
48 #define CPU_RELEASE_ADDR secondary_boot_func
50 /* Generic Timer Definitions */
51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
53 /* Size of malloc() pool */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
57 #define CONFIG_SYS_NS16550_SERIAL
58 #define CONFIG_SYS_NS16550_REG_SIZE 1
59 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
61 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
65 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
67 #define CONFIG_SPL_TEXT_BASE 0x10000000
68 #define CONFIG_SPL_MAX_SIZE 0x17000
69 #define CONFIG_SPL_STACK 0x1001e000
70 #define CONFIG_SPL_PAD_TO 0x1d000
72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
73 CONFIG_SPL_BSS_MAX_SIZE)
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
76 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
78 #ifdef CONFIG_SECURE_BOOT
79 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
81 * HDR would be appended at end of image and copied to DDR along
82 * with U-Boot image. Here u-boot max. size is 512K. So if binary
83 * size increases then increase this size in case of secure boot as
84 * it uses raw u-boot image instead of fit image.
86 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
88 #define CONFIG_SYS_MONITOR_LEN 0x100000
89 #endif /* ifdef CONFIG_SECURE_BOOT */
93 #ifdef CONFIG_NAND_BOOT
94 #define CONFIG_SPL_PBL_PAD
95 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
96 #define CONFIG_SPL_TEXT_BASE 0x10000000
97 #define CONFIG_SPL_MAX_SIZE 0x1a000
98 #define CONFIG_SPL_STACK 0x1001d000
99 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
100 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
101 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
102 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
103 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
104 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
106 #ifdef CONFIG_SECURE_BOOT
107 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
108 #endif /* ifdef CONFIG_SECURE_BOOT */
110 #ifdef CONFIG_U_BOOT_HDR_SIZE
112 * HDR would be appended at end of image and copied to DDR along
113 * with U-Boot image. Here u-boot max. size is 512K. So if binary
114 * size increases then increase this size in case of secure boot as
115 * it uses raw u-boot image instead of fit image.
117 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
119 #define CONFIG_SYS_MONITOR_LEN 0x100000
120 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
126 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
127 #define CONFIG_FSL_IFC
129 * CONFIG_SYS_FLASH_BASE has the final address (core view)
130 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
131 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
132 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
134 #define CONFIG_SYS_FLASH_BASE 0x60000000
135 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
136 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
138 #ifdef CONFIG_MTD_NOR_FLASH
139 #define CONFIG_FLASH_CFI_DRIVER
140 #define CONFIG_SYS_FLASH_CFI
141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142 #define CONFIG_SYS_FLASH_QUIET_TEST
143 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
149 #define CONFIG_SYS_I2C
153 #define CONFIG_PCIE1 /* PCIE controller 1 */
154 #define CONFIG_PCIE2 /* PCIE controller 2 */
155 #define CONFIG_PCIE3 /* PCIE controller 3 */
158 #define CONFIG_PCI_SCAN_SHOW
162 /* Command line configuration */
167 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
173 #define CONFIG_FSL_DSPI
174 #ifdef CONFIG_FSL_DSPI
175 #define CONFIG_DM_SPI_FLASH
176 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
177 #define CONFIG_SPI_FLASH_SST /* cs1 */
178 #define CONFIG_SPI_FLASH_EON /* cs2 */
179 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
180 #define CONFIG_SF_DEFAULT_BUS 1
181 #define CONFIG_SF_DEFAULT_CS 0
188 #define CONFIG_SYS_DPAA_FMAN
189 #ifdef CONFIG_SYS_DPAA_FMAN
190 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
192 #ifdef CONFIG_NAND_BOOT
193 /* Store Fman ucode at offeset 0x900000(72 blocks). */
194 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
195 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
196 #elif defined(CONFIG_SD_BOOT)
198 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
199 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
200 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
202 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
203 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
204 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
205 #elif defined(CONFIG_QSPI_BOOT)
206 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
207 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
208 #define CONFIG_ENV_SPI_BUS 0
209 #define CONFIG_ENV_SPI_CS 0
210 #define CONFIG_ENV_SPI_MAX_HZ 1000000
211 #define CONFIG_ENV_SPI_MODE 0x03
213 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
214 /* FMan fireware Pre-load address */
215 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
216 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
218 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
219 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
223 /* Miscellaneous configurable options */
224 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
226 #define CONFIG_HWCONFIG
227 #define HWCONFIG_BUFFER_SIZE 128
230 #ifndef CONFIG_SPL_BUILD
231 #define BOOT_TARGET_DEVICES(func) \
234 #include <config_distro_bootcmd.h>
237 /* Initial environment variables */
238 #define CONFIG_EXTRA_ENV_SETTINGS \
239 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
240 "fdt_high=0xffffffffffffffff\0" \
241 "initrd_high=0xffffffffffffffff\0" \
242 "fdt_addr=0x64f00000\0" \
243 "kernel_addr=0x61000000\0" \
244 "scriptaddr=0x80000000\0" \
245 "scripthdraddr=0x80080000\0" \
246 "fdtheader_addr_r=0x80100000\0" \
247 "kernelheader_addr_r=0x80200000\0" \
248 "kernel_addr_r=0x81000000\0" \
249 "fdt_addr_r=0x90000000\0" \
250 "load_addr=0xa0000000\0" \
251 "kernelheader_addr=0x60800000\0" \
252 "kernel_size=0x2800000\0" \
253 "kernelheader_size=0x40000\0" \
254 "kernel_addr_sd=0x8000\0" \
255 "kernel_size_sd=0x14000\0" \
256 "kernelhdr_addr_sd=0x4000\0" \
257 "kernelhdr_size_sd=0x10\0" \
258 "console=ttyS0,115200\0" \
260 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
262 "boot_scripts=ls1043ardb_boot.scr\0" \
263 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
264 "scan_dev_for_boot_part=" \
265 "part list ${devtype} ${devnum} devplist; " \
266 "env exists devplist || setenv devplist 1; " \
267 "for distro_bootpart in ${devplist}; do " \
268 "if fstype ${devtype} " \
269 "${devnum}:${distro_bootpart} " \
270 "bootfstype; then " \
271 "run scan_dev_for_boot; " \
274 "scan_dev_for_boot=" \
275 "echo Scanning ${devtype} " \
276 "${devnum}:${distro_bootpart}...; " \
277 "for prefix in ${boot_prefixes}; do " \
278 "run scan_dev_for_scripts; " \
281 "load ${devtype} ${devnum}:${distro_bootpart} " \
282 "${scriptaddr} ${prefix}${script}; " \
283 "env exists secureboot && load ${devtype} " \
284 "${devnum}:${distro_bootpart} " \
285 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
286 "&& esbc_validate ${scripthdraddr};" \
287 "source ${scriptaddr}\0" \
288 "qspi_bootcmd=echo Trying load from qspi..;" \
289 "sf probe && sf read $load_addr " \
290 "$kernel_addr $kernel_size; env exists secureboot " \
291 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
292 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
293 "bootm $load_addr#$board\0" \
294 "nor_bootcmd=echo Trying load from nor..;" \
295 "cp.b $kernel_addr $load_addr " \
296 "$kernel_size; env exists secureboot " \
297 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
298 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
299 "bootm $load_addr#$board\0" \
300 "sd_bootcmd=echo Trying load from SD ..;" \
301 "mmcinfo; mmc read $load_addr " \
302 "$kernel_addr_sd $kernel_size_sd && " \
303 "env exists secureboot && mmc read $kernelheader_addr_r " \
304 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
305 " && esbc_validate ${kernelheader_addr_r};" \
306 "bootm $load_addr#$board\0"
309 #undef CONFIG_BOOTCOMMAND
310 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
311 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
312 "env exists secureboot && esbc_halt;"
313 #elif defined(CONFIG_SD_BOOT)
314 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
315 "env exists secureboot && esbc_halt;"
317 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
318 "env exists secureboot && esbc_halt;"
322 /* Monitor Command Prompt */
323 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
325 #define CONFIG_SYS_MAXARGS 64 /* max command args */
327 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
329 #include <asm/arch/soc.h>
331 #endif /* __LS1043A_COMMON_H */