1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
29 #include <asm/arch/stream_id_lsch2.h>
30 #include <asm/arch/config.h>
32 /* Link Definitions */
34 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 #define CONFIG_VERY_BIG_RAM
40 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
41 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
42 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
43 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
45 #define CPU_RELEASE_ADDR secondary_boot_addr
47 /* Generic Timer Definitions */
48 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE 1
53 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
58 #define CONFIG_SPL_MAX_SIZE 0x17000
59 #define CONFIG_SPL_STACK 0x1001e000
60 #define CONFIG_SPL_PAD_TO 0x1d000
62 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
63 CONFIG_SPL_BSS_MAX_SIZE)
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
66 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
68 #ifdef CONFIG_NXP_ESBC
69 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
71 * HDR would be appended at end of image and copied to DDR along
72 * with U-Boot image. Here u-boot max. size is 512K. So if binary
73 * size increases then increase this size in case of secure boot as
74 * it uses raw u-boot image instead of fit image.
76 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
78 #define CONFIG_SYS_MONITOR_LEN 0x100000
79 #endif /* ifdef CONFIG_NXP_ESBC */
83 #ifdef CONFIG_NAND_BOOT
84 #define CONFIG_SPL_PBL_PAD
85 #define CONFIG_SPL_MAX_SIZE 0x1a000
86 #define CONFIG_SPL_STACK 0x1001d000
87 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
88 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
89 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
90 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
94 #ifdef CONFIG_NXP_ESBC
95 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
96 #endif /* ifdef CONFIG_NXP_ESBC */
98 #ifdef CONFIG_U_BOOT_HDR_SIZE
100 * HDR would be appended at end of image and copied to DDR along
101 * with U-Boot image. Here u-boot max. size is 512K. So if binary
102 * size increases then increase this size in case of secure boot as
103 * it uses raw u-boot image instead of fit image.
105 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
107 #define CONFIG_SYS_MONITOR_LEN 0x100000
108 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
116 #if defined(CONFIG_TFABOOT) || \
117 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
119 * CONFIG_SYS_FLASH_BASE has the final address (core view)
120 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
121 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
122 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
124 #define CONFIG_SYS_FLASH_BASE 0x60000000
125 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
126 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
128 #ifdef CONFIG_MTD_NOR_FLASH
129 #define CONFIG_SYS_FLASH_QUIET_TEST
130 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
139 #define CONFIG_PCIE1 /* PCIE controller 1 */
140 #define CONFIG_PCIE2 /* PCIE controller 2 */
141 #define CONFIG_PCIE3 /* PCIE controller 3 */
144 #define CONFIG_PCI_SCAN_SHOW
152 #define CONFIG_SYS_DPAA_FMAN
153 #ifdef CONFIG_SYS_DPAA_FMAN
154 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
156 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
160 /* Miscellaneous configurable options */
162 #define CONFIG_HWCONFIG
163 #define HWCONFIG_BUFFER_SIZE 128
166 #ifndef CONFIG_SPL_BUILD
167 #define BOOT_TARGET_DEVICES(func) \
171 #include <config_distro_bootcmd.h>
174 /* Initial environment variables */
175 #define CONFIG_EXTRA_ENV_SETTINGS \
176 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
177 "fdt_high=0xffffffffffffffff\0" \
178 "initrd_high=0xffffffffffffffff\0" \
179 "fdt_addr=0x64f00000\0" \
180 "kernel_addr=0x61000000\0" \
181 "scriptaddr=0x80000000\0" \
182 "scripthdraddr=0x80080000\0" \
183 "fdtheader_addr_r=0x80100000\0" \
184 "kernelheader_addr_r=0x80200000\0" \
185 "kernel_addr_r=0x81000000\0" \
186 "kernel_start=0x1000000\0" \
187 "kernelheader_start=0x800000\0" \
188 "fdt_addr_r=0x90000000\0" \
189 "load_addr=0xa0000000\0" \
190 "kernelheader_addr=0x60600000\0" \
191 "kernel_size=0x2800000\0" \
192 "kernelheader_size=0x40000\0" \
193 "kernel_addr_sd=0x8000\0" \
194 "kernel_size_sd=0x14000\0" \
195 "kernelhdr_addr_sd=0x3000\0" \
196 "kernelhdr_size_sd=0x10\0" \
197 "console=ttyS0,115200\0" \
199 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
201 "boot_scripts=ls1043ardb_boot.scr\0" \
202 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
203 "scan_dev_for_boot_part=" \
204 "part list ${devtype} ${devnum} devplist; " \
205 "env exists devplist || setenv devplist 1; " \
206 "for distro_bootpart in ${devplist}; do " \
207 "if fstype ${devtype} " \
208 "${devnum}:${distro_bootpart} " \
209 "bootfstype; then " \
210 "run scan_dev_for_boot; " \
214 "load ${devtype} ${devnum}:${distro_bootpart} " \
215 "${scriptaddr} ${prefix}${script}; " \
216 "env exists secureboot && load ${devtype} " \
217 "${devnum}:${distro_bootpart} " \
218 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
219 "env exists secureboot " \
220 "&& esbc_validate ${scripthdraddr};" \
221 "source ${scriptaddr}\0" \
222 "qspi_bootcmd=echo Trying load from qspi..;" \
223 "sf probe && sf read $load_addr " \
224 "$kernel_start $kernel_size; env exists secureboot " \
225 "&& sf read $kernelheader_addr_r $kernelheader_start " \
226 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
227 "bootm $load_addr#$board\0" \
228 "nor_bootcmd=echo Trying load from nor..;" \
229 "cp.b $kernel_addr $load_addr " \
230 "$kernel_size; env exists secureboot " \
231 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
232 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
233 "bootm $load_addr#$board\0" \
234 "nand_bootcmd=echo Trying load from NAND..;" \
235 "nand info; nand read $load_addr " \
236 "$kernel_start $kernel_size; env exists secureboot " \
237 "&& nand read $kernelheader_addr_r $kernelheader_start " \
238 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
239 "bootm $load_addr#$board\0" \
240 "sd_bootcmd=echo Trying load from SD ..;" \
241 "mmcinfo; mmc read $load_addr " \
242 "$kernel_addr_sd $kernel_size_sd && " \
243 "env exists secureboot && mmc read $kernelheader_addr_r " \
244 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
245 " && esbc_validate ${kernelheader_addr_r};" \
246 "bootm $load_addr#$board\0"
249 #ifdef CONFIG_TFABOOT
250 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
251 "env exists secureboot && esbc_halt;"
252 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
253 "env exists secureboot && esbc_halt;"
254 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
255 "env exists secureboot && esbc_halt;"
256 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
257 "env exists secureboot && esbc_halt;"
261 /* Monitor Command Prompt */
262 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
264 #define CONFIG_SYS_MAXARGS 64 /* max command args */
266 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
268 #include <asm/arch/soc.h>
270 #endif /* __LS1043A_COMMON_H */