1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
29 #define CONFIG_REMAKE_ELF
31 #include <asm/arch/stream_id_lsch2.h>
32 #include <asm/arch/config.h>
34 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
41 #define CONFIG_VERY_BIG_RAM
42 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
43 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
44 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
45 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
47 #define CPU_RELEASE_ADDR secondary_boot_addr
49 /* Generic Timer Definitions */
50 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
53 #define CONFIG_SYS_NS16550_SERIAL
54 #define CONFIG_SYS_NS16550_REG_SIZE 1
55 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
60 #define CONFIG_SPL_MAX_SIZE 0x17000
61 #define CONFIG_SPL_STACK 0x1001e000
62 #define CONFIG_SPL_PAD_TO 0x1d000
64 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
65 CONFIG_SPL_BSS_MAX_SIZE)
66 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
67 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
68 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
70 #ifdef CONFIG_NXP_ESBC
71 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
73 * HDR would be appended at end of image and copied to DDR along
74 * with U-Boot image. Here u-boot max. size is 512K. So if binary
75 * size increases then increase this size in case of secure boot as
76 * it uses raw u-boot image instead of fit image.
78 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
80 #define CONFIG_SYS_MONITOR_LEN 0x100000
81 #endif /* ifdef CONFIG_NXP_ESBC */
85 #ifdef CONFIG_NAND_BOOT
86 #define CONFIG_SPL_PBL_PAD
87 #define CONFIG_SPL_MAX_SIZE 0x1a000
88 #define CONFIG_SPL_STACK 0x1001d000
89 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
90 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
91 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
93 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
94 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
96 #ifdef CONFIG_NXP_ESBC
97 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
98 #endif /* ifdef CONFIG_NXP_ESBC */
100 #ifdef CONFIG_U_BOOT_HDR_SIZE
102 * HDR would be appended at end of image and copied to DDR along
103 * with U-Boot image. Here u-boot max. size is 512K. So if binary
104 * size increases then increase this size in case of secure boot as
105 * it uses raw u-boot image instead of fit image.
107 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
109 #define CONFIG_SYS_MONITOR_LEN 0x100000
110 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
115 #ifdef CONFIG_DM_GPIO
116 #ifndef CONFIG_MPC8XXX_GPIO
117 #define CONFIG_MPC8XXX_GPIO
123 #if defined(CONFIG_TFABOOT) || \
124 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
125 #define CONFIG_FSL_IFC
127 * CONFIG_SYS_FLASH_BASE has the final address (core view)
128 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
129 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
130 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
132 #define CONFIG_SYS_FLASH_BASE 0x60000000
133 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
134 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
136 #ifdef CONFIG_MTD_NOR_FLASH
137 #define CONFIG_SYS_FLASH_QUIET_TEST
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
147 #define CONFIG_PCIE1 /* PCIE controller 1 */
148 #define CONFIG_PCIE2 /* PCIE controller 2 */
149 #define CONFIG_PCIE3 /* PCIE controller 3 */
152 #define CONFIG_PCI_SCAN_SHOW
158 #ifdef CONFIG_FSL_DSPI
159 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
160 #define CONFIG_SPI_FLASH_SST /* cs1 */
161 #define CONFIG_SPI_FLASH_EON /* cs2 */
167 #define CONFIG_SYS_DPAA_FMAN
168 #ifdef CONFIG_SYS_DPAA_FMAN
169 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
171 #ifdef CONFIG_TFABOOT
172 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
173 #define CONFIG_SYS_QE_FW_ADDR 0x940000
177 #if defined(CONFIG_SD_BOOT)
179 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
180 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
181 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
183 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
184 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
185 #elif defined(CONFIG_QSPI_BOOT)
186 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
188 /* FMan fireware Pre-load address */
189 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
190 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
193 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
194 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
198 /* Miscellaneous configurable options */
200 #define CONFIG_HWCONFIG
201 #define HWCONFIG_BUFFER_SIZE 128
204 #ifndef CONFIG_SPL_BUILD
205 #define BOOT_TARGET_DEVICES(func) \
209 #include <config_distro_bootcmd.h>
212 /* Initial environment variables */
213 #define CONFIG_EXTRA_ENV_SETTINGS \
214 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
215 "fdt_high=0xffffffffffffffff\0" \
216 "initrd_high=0xffffffffffffffff\0" \
217 "fdt_addr=0x64f00000\0" \
218 "kernel_addr=0x61000000\0" \
219 "scriptaddr=0x80000000\0" \
220 "scripthdraddr=0x80080000\0" \
221 "fdtheader_addr_r=0x80100000\0" \
222 "kernelheader_addr_r=0x80200000\0" \
223 "kernel_addr_r=0x81000000\0" \
224 "kernel_start=0x1000000\0" \
225 "kernelheader_start=0x800000\0" \
226 "fdt_addr_r=0x90000000\0" \
227 "load_addr=0xa0000000\0" \
228 "kernelheader_addr=0x60600000\0" \
229 "kernel_size=0x2800000\0" \
230 "kernelheader_size=0x40000\0" \
231 "kernel_addr_sd=0x8000\0" \
232 "kernel_size_sd=0x14000\0" \
233 "kernelhdr_addr_sd=0x3000\0" \
234 "kernelhdr_size_sd=0x10\0" \
235 "console=ttyS0,115200\0" \
237 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
239 "boot_scripts=ls1043ardb_boot.scr\0" \
240 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
241 "scan_dev_for_boot_part=" \
242 "part list ${devtype} ${devnum} devplist; " \
243 "env exists devplist || setenv devplist 1; " \
244 "for distro_bootpart in ${devplist}; do " \
245 "if fstype ${devtype} " \
246 "${devnum}:${distro_bootpart} " \
247 "bootfstype; then " \
248 "run scan_dev_for_boot; " \
252 "load ${devtype} ${devnum}:${distro_bootpart} " \
253 "${scriptaddr} ${prefix}${script}; " \
254 "env exists secureboot && load ${devtype} " \
255 "${devnum}:${distro_bootpart} " \
256 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
257 "env exists secureboot " \
258 "&& esbc_validate ${scripthdraddr};" \
259 "source ${scriptaddr}\0" \
260 "qspi_bootcmd=echo Trying load from qspi..;" \
261 "sf probe && sf read $load_addr " \
262 "$kernel_start $kernel_size; env exists secureboot " \
263 "&& sf read $kernelheader_addr_r $kernelheader_start " \
264 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
265 "bootm $load_addr#$board\0" \
266 "nor_bootcmd=echo Trying load from nor..;" \
267 "cp.b $kernel_addr $load_addr " \
268 "$kernel_size; env exists secureboot " \
269 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
270 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
271 "bootm $load_addr#$board\0" \
272 "nand_bootcmd=echo Trying load from NAND..;" \
273 "nand info; nand read $load_addr " \
274 "$kernel_start $kernel_size; env exists secureboot " \
275 "&& nand read $kernelheader_addr_r $kernelheader_start " \
276 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
277 "bootm $load_addr#$board\0" \
278 "sd_bootcmd=echo Trying load from SD ..;" \
279 "mmcinfo; mmc read $load_addr " \
280 "$kernel_addr_sd $kernel_size_sd && " \
281 "env exists secureboot && mmc read $kernelheader_addr_r " \
282 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
283 " && esbc_validate ${kernelheader_addr_r};" \
284 "bootm $load_addr#$board\0"
287 #undef CONFIG_BOOTCOMMAND
288 #ifdef CONFIG_TFABOOT
289 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
290 "env exists secureboot && esbc_halt;"
291 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
292 "env exists secureboot && esbc_halt;"
293 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
294 "env exists secureboot && esbc_halt;"
295 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
296 "env exists secureboot && esbc_halt;"
298 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
299 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
300 "env exists secureboot && esbc_halt;"
301 #elif defined(CONFIG_SD_BOOT)
302 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
303 "env exists secureboot && esbc_halt;"
305 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
306 "env exists secureboot && esbc_halt;"
311 /* Monitor Command Prompt */
312 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
314 #define CONFIG_SYS_MAXARGS 64 /* max command args */
316 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
318 #include <asm/arch/soc.h>
320 #endif /* __LS1043A_COMMON_H */