1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor
6 #ifndef __LS1043A_COMMON_H
7 #define __LS1043A_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
21 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
24 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
28 #define CONFIG_REMAKE_ELF
29 #define CONFIG_FSL_LAYERSCAPE
32 #include <asm/arch/stream_id_lsch2.h>
33 #include <asm/arch/config.h>
35 /* Link Definitions */
37 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
42 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_VERY_BIG_RAM
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
50 #define CPU_RELEASE_ADDR secondary_boot_func
52 /* Generic Timer Definitions */
53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
55 /* Size of malloc() pool */
56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
59 #define CONFIG_SYS_NS16550_SERIAL
60 #define CONFIG_SYS_NS16550_REG_SIZE 1
61 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
68 #define CONFIG_SPL_TEXT_BASE 0x10000000
69 #define CONFIG_SPL_MAX_SIZE 0x17000
70 #define CONFIG_SPL_STACK 0x1001e000
71 #define CONFIG_SPL_PAD_TO 0x1d000
73 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
74 CONFIG_SPL_BSS_MAX_SIZE)
75 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
76 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
77 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
79 #ifdef CONFIG_SECURE_BOOT
80 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
82 * HDR would be appended at end of image and copied to DDR along
83 * with U-Boot image. Here u-boot max. size is 512K. So if binary
84 * size increases then increase this size in case of secure boot as
85 * it uses raw u-boot image instead of fit image.
87 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
89 #define CONFIG_SYS_MONITOR_LEN 0x100000
90 #endif /* ifdef CONFIG_SECURE_BOOT */
94 #ifdef CONFIG_NAND_BOOT
95 #define CONFIG_SPL_PBL_PAD
96 #define CONFIG_SPL_TEXT_BASE 0x10000000
97 #define CONFIG_SPL_MAX_SIZE 0x1a000
98 #define CONFIG_SPL_STACK 0x1001d000
99 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
100 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
101 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
102 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
103 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
104 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
106 #ifdef CONFIG_SECURE_BOOT
107 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
108 #endif /* ifdef CONFIG_SECURE_BOOT */
110 #ifdef CONFIG_U_BOOT_HDR_SIZE
112 * HDR would be appended at end of image and copied to DDR along
113 * with U-Boot image. Here u-boot max. size is 512K. So if binary
114 * size increases then increase this size in case of secure boot as
115 * it uses raw u-boot image instead of fit image.
117 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
119 #define CONFIG_SYS_MONITOR_LEN 0x100000
120 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
126 #if defined(CONFIG_TFABOOT) || \
127 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
128 #define CONFIG_FSL_IFC
130 * CONFIG_SYS_FLASH_BASE has the final address (core view)
131 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
132 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
133 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
135 #define CONFIG_SYS_FLASH_BASE 0x60000000
136 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
137 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
139 #ifdef CONFIG_MTD_NOR_FLASH
140 #define CONFIG_SYS_FLASH_QUIET_TEST
141 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
147 #define CONFIG_SYS_I2C
151 #define CONFIG_PCIE1 /* PCIE controller 1 */
152 #define CONFIG_PCIE2 /* PCIE controller 2 */
153 #define CONFIG_PCIE3 /* PCIE controller 3 */
156 #define CONFIG_PCI_SCAN_SHOW
160 /* Command line configuration */
165 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
171 #define CONFIG_FSL_DSPI
172 #ifdef CONFIG_FSL_DSPI
173 #define CONFIG_DM_SPI_FLASH
174 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
175 #define CONFIG_SPI_FLASH_SST /* cs1 */
176 #define CONFIG_SPI_FLASH_EON /* cs2 */
177 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
178 #define CONFIG_SF_DEFAULT_BUS 1
179 #define CONFIG_SF_DEFAULT_CS 0
186 #define CONFIG_SYS_DPAA_FMAN
187 #ifdef CONFIG_SYS_DPAA_FMAN
188 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
190 #ifdef CONFIG_TFABOOT
191 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
192 #define CONFIG_SYS_QE_FW_ADDR 0x940000
194 #define CONFIG_ENV_SPI_BUS 0
195 #define CONFIG_ENV_SPI_CS 0
196 #define CONFIG_ENV_SPI_MAX_HZ 1000000
197 #define CONFIG_ENV_SPI_MODE 0x03
200 #ifdef CONFIG_NAND_BOOT
201 /* Store Fman ucode at offeset 0x900000(72 blocks). */
202 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
203 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
204 #elif defined(CONFIG_SD_BOOT)
206 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
207 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
208 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
210 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
211 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
212 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
213 #elif defined(CONFIG_QSPI_BOOT)
214 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
215 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
216 #define CONFIG_ENV_SPI_BUS 0
217 #define CONFIG_ENV_SPI_CS 0
218 #define CONFIG_ENV_SPI_MAX_HZ 1000000
219 #define CONFIG_ENV_SPI_MODE 0x03
221 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
222 /* FMan fireware Pre-load address */
223 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
224 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
227 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
228 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
232 /* Miscellaneous configurable options */
233 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
235 #define CONFIG_HWCONFIG
236 #define HWCONFIG_BUFFER_SIZE 128
239 #ifndef CONFIG_SPL_BUILD
240 #define BOOT_TARGET_DEVICES(func) \
243 #include <config_distro_bootcmd.h>
246 /* Initial environment variables */
247 #define CONFIG_EXTRA_ENV_SETTINGS \
248 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
249 "fdt_high=0xffffffffffffffff\0" \
250 "initrd_high=0xffffffffffffffff\0" \
251 "fdt_addr=0x64f00000\0" \
252 "kernel_addr=0x61000000\0" \
253 "scriptaddr=0x80000000\0" \
254 "scripthdraddr=0x80080000\0" \
255 "fdtheader_addr_r=0x80100000\0" \
256 "kernelheader_addr_r=0x80200000\0" \
257 "kernel_addr_r=0x81000000\0" \
258 "fdt_addr_r=0x90000000\0" \
259 "load_addr=0xa0000000\0" \
260 "kernelheader_addr=0x60800000\0" \
261 "kernel_size=0x2800000\0" \
262 "kernelheader_size=0x40000\0" \
263 "kernel_addr_sd=0x8000\0" \
264 "kernel_size_sd=0x14000\0" \
265 "kernelhdr_addr_sd=0x4000\0" \
266 "kernelhdr_size_sd=0x10\0" \
267 "console=ttyS0,115200\0" \
269 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
271 "boot_scripts=ls1043ardb_boot.scr\0" \
272 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
273 "scan_dev_for_boot_part=" \
274 "part list ${devtype} ${devnum} devplist; " \
275 "env exists devplist || setenv devplist 1; " \
276 "for distro_bootpart in ${devplist}; do " \
277 "if fstype ${devtype} " \
278 "${devnum}:${distro_bootpart} " \
279 "bootfstype; then " \
280 "run scan_dev_for_boot; " \
283 "scan_dev_for_boot=" \
284 "echo Scanning ${devtype} " \
285 "${devnum}:${distro_bootpart}...; " \
286 "for prefix in ${boot_prefixes}; do " \
287 "run scan_dev_for_scripts; " \
290 "load ${devtype} ${devnum}:${distro_bootpart} " \
291 "${scriptaddr} ${prefix}${script}; " \
292 "env exists secureboot && load ${devtype} " \
293 "${devnum}:${distro_bootpart} " \
294 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
295 "&& esbc_validate ${scripthdraddr};" \
296 "source ${scriptaddr}\0" \
297 "qspi_bootcmd=echo Trying load from qspi..;" \
298 "sf probe && sf read $load_addr " \
299 "$kernel_addr $kernel_size; env exists secureboot " \
300 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
301 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
302 "bootm $load_addr#$board\0" \
303 "nor_bootcmd=echo Trying load from nor..;" \
304 "cp.b $kernel_addr $load_addr " \
305 "$kernel_size; env exists secureboot " \
306 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
307 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
308 "bootm $load_addr#$board\0" \
309 "sd_bootcmd=echo Trying load from SD ..;" \
310 "mmcinfo; mmc read $load_addr " \
311 "$kernel_addr_sd $kernel_size_sd && " \
312 "env exists secureboot && mmc read $kernelheader_addr_r " \
313 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
314 " && esbc_validate ${kernelheader_addr_r};" \
315 "bootm $load_addr#$board\0"
318 #undef CONFIG_BOOTCOMMAND
319 #ifdef CONFIG_TFABOOT
320 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
321 "env exists secureboot && esbc_halt;"
322 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
323 "env exists secureboot && esbc_halt;"
324 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
325 "env exists secureboot && esbc_halt;"
326 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
327 "env exists secureboot && esbc_halt;"
329 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
330 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
331 "env exists secureboot && esbc_halt;"
332 #elif defined(CONFIG_SD_BOOT)
333 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
334 "env exists secureboot && esbc_halt;"
336 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
337 "env exists secureboot && esbc_halt;"
342 /* Monitor Command Prompt */
343 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
345 #define CONFIG_SYS_MAXARGS 64 /* max command args */
347 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
349 #include <asm/arch/soc.h>
351 #endif /* __LS1043A_COMMON_H */