1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor
6 #ifndef __LS1043A_COMMON_H
7 #define __LS1043A_COMMON_H
10 #ifdef CONFIG_SPL_BUILD
21 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
24 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
28 #define CONFIG_REMAKE_ELF
31 #include <asm/arch/stream_id_lsch2.h>
32 #include <asm/arch/config.h>
34 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
41 #define CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_VERY_BIG_RAM
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
49 #define CPU_RELEASE_ADDR secondary_boot_func
51 /* Generic Timer Definitions */
52 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
54 /* Size of malloc() pool */
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE 1
60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
67 #define CONFIG_SPL_MAX_SIZE 0x17000
68 #define CONFIG_SPL_STACK 0x1001e000
69 #define CONFIG_SPL_PAD_TO 0x1d000
71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
72 CONFIG_SPL_BSS_MAX_SIZE)
73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
74 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
75 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
77 #ifdef CONFIG_SECURE_BOOT
78 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
80 * HDR would be appended at end of image and copied to DDR along
81 * with U-Boot image. Here u-boot max. size is 512K. So if binary
82 * size increases then increase this size in case of secure boot as
83 * it uses raw u-boot image instead of fit image.
85 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
87 #define CONFIG_SYS_MONITOR_LEN 0x100000
88 #endif /* ifdef CONFIG_SECURE_BOOT */
92 #ifdef CONFIG_NAND_BOOT
93 #define CONFIG_SPL_PBL_PAD
94 #define CONFIG_SPL_MAX_SIZE 0x1a000
95 #define CONFIG_SPL_STACK 0x1001d000
96 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
97 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
98 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
99 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
100 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
101 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
103 #ifdef CONFIG_SECURE_BOOT
104 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
105 #endif /* ifdef CONFIG_SECURE_BOOT */
107 #ifdef CONFIG_U_BOOT_HDR_SIZE
109 * HDR would be appended at end of image and copied to DDR along
110 * with U-Boot image. Here u-boot max. size is 512K. So if binary
111 * size increases then increase this size in case of secure boot as
112 * it uses raw u-boot image instead of fit image.
114 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
116 #define CONFIG_SYS_MONITOR_LEN 0x100000
117 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
123 #if defined(CONFIG_TFABOOT) || \
124 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
125 #define CONFIG_FSL_IFC
127 * CONFIG_SYS_FLASH_BASE has the final address (core view)
128 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
129 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
130 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
132 #define CONFIG_SYS_FLASH_BASE 0x60000000
133 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
134 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
136 #ifdef CONFIG_MTD_NOR_FLASH
137 #define CONFIG_SYS_FLASH_QUIET_TEST
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
144 #define CONFIG_SYS_I2C
148 #define CONFIG_PCIE1 /* PCIE controller 1 */
149 #define CONFIG_PCIE2 /* PCIE controller 2 */
150 #define CONFIG_PCIE3 /* PCIE controller 3 */
153 #define CONFIG_PCI_SCAN_SHOW
157 /* Command line configuration */
162 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
168 #define CONFIG_FSL_DSPI
169 #ifdef CONFIG_FSL_DSPI
170 #define CONFIG_DM_SPI_FLASH
171 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
172 #define CONFIG_SPI_FLASH_SST /* cs1 */
173 #define CONFIG_SPI_FLASH_EON /* cs2 */
179 #define CONFIG_SYS_DPAA_FMAN
180 #ifdef CONFIG_SYS_DPAA_FMAN
181 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
183 #ifdef CONFIG_TFABOOT
184 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
185 #define CONFIG_SYS_QE_FW_ADDR 0x940000
189 #ifdef CONFIG_NAND_BOOT
190 /* Store Fman ucode at offeset 0x900000(72 blocks). */
191 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
192 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
193 #elif defined(CONFIG_SD_BOOT)
195 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
196 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
197 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
199 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
200 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
201 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
202 #elif defined(CONFIG_QSPI_BOOT)
203 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
204 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
206 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
207 /* FMan fireware Pre-load address */
208 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
209 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
212 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
213 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
217 /* Miscellaneous configurable options */
218 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
220 #define CONFIG_HWCONFIG
221 #define HWCONFIG_BUFFER_SIZE 128
224 #ifndef CONFIG_SPL_BUILD
225 #define BOOT_TARGET_DEVICES(func) \
229 #include <config_distro_bootcmd.h>
232 /* Initial environment variables */
233 #define CONFIG_EXTRA_ENV_SETTINGS \
234 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
235 "fdt_high=0xffffffffffffffff\0" \
236 "initrd_high=0xffffffffffffffff\0" \
237 "fdt_addr=0x64f00000\0" \
238 "kernel_addr=0x61000000\0" \
239 "scriptaddr=0x80000000\0" \
240 "scripthdraddr=0x80080000\0" \
241 "fdtheader_addr_r=0x80100000\0" \
242 "kernelheader_addr_r=0x80200000\0" \
243 "kernel_addr_r=0x81000000\0" \
244 "kernel_start=0x1000000\0" \
245 "kernelheader_start=0x800000\0" \
246 "fdt_addr_r=0x90000000\0" \
247 "load_addr=0xa0000000\0" \
248 "kernelheader_addr=0x60800000\0" \
249 "kernel_size=0x2800000\0" \
250 "kernelheader_size=0x40000\0" \
251 "kernel_addr_sd=0x8000\0" \
252 "kernel_size_sd=0x14000\0" \
253 "kernelhdr_addr_sd=0x4000\0" \
254 "kernelhdr_size_sd=0x10\0" \
255 "console=ttyS0,115200\0" \
257 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
259 "boot_scripts=ls1043ardb_boot.scr\0" \
260 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
261 "scan_dev_for_boot_part=" \
262 "part list ${devtype} ${devnum} devplist; " \
263 "env exists devplist || setenv devplist 1; " \
264 "for distro_bootpart in ${devplist}; do " \
265 "if fstype ${devtype} " \
266 "${devnum}:${distro_bootpart} " \
267 "bootfstype; then " \
268 "run scan_dev_for_boot; " \
272 "load ${devtype} ${devnum}:${distro_bootpart} " \
273 "${scriptaddr} ${prefix}${script}; " \
274 "env exists secureboot && load ${devtype} " \
275 "${devnum}:${distro_bootpart} " \
276 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
277 "env exists secureboot " \
278 "&& esbc_validate ${scripthdraddr};" \
279 "source ${scriptaddr}\0" \
280 "qspi_bootcmd=echo Trying load from qspi..;" \
281 "sf probe && sf read $load_addr " \
282 "$kernel_addr $kernel_size; env exists secureboot " \
283 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
284 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
285 "bootm $load_addr#$board\0" \
286 "nor_bootcmd=echo Trying load from nor..;" \
287 "cp.b $kernel_addr $load_addr " \
288 "$kernel_size; env exists secureboot " \
289 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
290 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
291 "bootm $load_addr#$board\0" \
292 "nand_bootcmd=echo Trying load from NAND..;" \
293 "nand info; nand read $load_addr " \
294 "$kernel_start $kernel_size; env exists secureboot " \
295 "&& nand read $kernelheader_addr_r $kernelheader_start " \
296 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
297 "bootm $load_addr#$board\0" \
298 "sd_bootcmd=echo Trying load from SD ..;" \
299 "mmcinfo; mmc read $load_addr " \
300 "$kernel_addr_sd $kernel_size_sd && " \
301 "env exists secureboot && mmc read $kernelheader_addr_r " \
302 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
303 " && esbc_validate ${kernelheader_addr_r};" \
304 "bootm $load_addr#$board\0"
307 #undef CONFIG_BOOTCOMMAND
308 #ifdef CONFIG_TFABOOT
309 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
310 "env exists secureboot && esbc_halt;"
311 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
312 "env exists secureboot && esbc_halt;"
313 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
314 "env exists secureboot && esbc_halt;"
315 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
316 "env exists secureboot && esbc_halt;"
318 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
319 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
320 "env exists secureboot && esbc_halt;"
321 #elif defined(CONFIG_SD_BOOT)
322 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
323 "env exists secureboot && esbc_halt;"
325 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
326 "env exists secureboot && esbc_halt;"
331 /* Monitor Command Prompt */
332 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
334 #define CONFIG_SYS_MAXARGS 64 /* max command args */
336 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
338 #include <asm/arch/soc.h>
340 #endif /* __LS1043A_COMMON_H */