include/configs/ls1028ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #ifndef __LS1028A_RDB_H
   7 #define __LS1028A_RDB_H
   8
   9 #include "ls1028a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12 #define CONFIG_DDR_CLK_FREQ             100000000
  13 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ / 4)
  14
  15 #define CONFIG_SYS_RTC_BUS_NUM         0
  16
  17 /* Store environment at top of flash */
  18
  19 #define CONFIG_DIMM_SLOTS_PER_CTLR          1
  20
  21 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  22
  23 #define CONFIG_QIXIS_I2C_ACCESS
  24
  25 /*
  26  * QIXIS Definitions
  27  */
  28 #define CONFIG_FSL_QIXIS
  29
  30 #ifdef CONFIG_FSL_QIXIS
  31 #define QIXIS_BASE                      0x7fb00000
  32 #define QIXIS_BASE_PHYS                 QIXIS_BASE
  33 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  34 #define QIXIS_LBMAP_SWITCH              2
  35 #define QIXIS_LBMAP_MASK                0xe0
  36 #define QIXIS_LBMAP_SHIFT               0x5
  37 #define QIXIS_LBMAP_DFLTBANK            0x00
  38 #define QIXIS_LBMAP_ALTBANK             0x00
  39 #define QIXIS_LBMAP_SD                  0x00
  40 #define QIXIS_LBMAP_EMMC                0x00
  41 #define QIXIS_LBMAP_QSPI                0x00
  42 #define QIXIS_RCW_SRC_SD                0xf8
  43 #define QIXIS_RCW_SRC_EMMC              0xf9
  44 #define QIXIS_RCW_SRC_QSPI              0xff
  45 #define QIXIS_RST_CTL_RESET             0x31
  46 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x10
  47 #define QIXIS_RCFG_CTL_RECONFIG_START   0x11
  48 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
  49 #define QIXIS_RST_FORCE_MEM             0x01
  50
  51 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  53                                         CSPR_PORT_SIZE_8 | \
  54                                         CSPR_MSEL_GPCM | \
  55                                         CSPR_V)
  56 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
  57                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
  58                                         CSOR_NOR_TRHZ_80)
  59 #endif
  60
  61 /* SATA */
  62 #ifndef CONFIG_CMD_EXT2
  63 #define CONFIG_CMD_EXT2
  64 #endif
  65 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  66 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  67 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  68                                                 CONFIG_SYS_SCSI_MAX_LUN)
  69 #define SCSI_VEND_ID 0x1b4b
  70 #define SCSI_DEV_ID  0x9170
  71 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
  72 #define CONFIG_SCSI_AHCI_PLAT
  73 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  74
  75 #endif /* __LS1028A_RDB_H */