1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __LS1028A_RDB_H
7 #define __LS1028A_RDB_H
9 #include "ls1028a_common.h"
11 #define CONFIG_SYS_CLK_FREQ 100000000
12 #define CONFIG_DDR_CLK_FREQ 100000000
13 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
15 #define CONFIG_SYS_RTC_BUS_NUM 0
17 /* Store environment at top of flash */
18 #define CONFIG_ENV_SIZE 0x2000
20 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_QIXIS_I2C_ACCESS
25 #define CONFIG_SYS_I2C_EARLY_INIT
30 #define CONFIG_FSL_QIXIS
32 #ifdef CONFIG_FSL_QIXIS
33 #define QIXIS_BASE 0x7fb00000
34 #define QIXIS_BASE_PHYS QIXIS_BASE
35 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
36 #define QIXIS_LBMAP_SWITCH 2
37 #define QIXIS_LBMAP_MASK 0xe0
38 #define QIXIS_LBMAP_SHIFT 0x5
39 #define QIXIS_LBMAP_DFLTBANK 0x00
40 #define QIXIS_LBMAP_ALTBANK 0x00
41 #define QIXIS_LBMAP_SD 0x00
42 #define QIXIS_LBMAP_EMMC 0x00
43 #define QIXIS_LBMAP_QSPI 0x00
44 #define QIXIS_RCW_SRC_SD 0xf8
45 #define QIXIS_RCW_SRC_EMMC 0xf9
46 #define QIXIS_RCW_SRC_QSPI 0xff
47 #define QIXIS_RST_CTL_RESET 0x31
48 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
49 #define QIXIS_RCFG_CTL_RECONFIG_START 0x11
50 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
51 #define QIXIS_RST_FORCE_MEM 0x01
53 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
54 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
58 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
59 CSOR_NOR_NOR_MODE_AVD_NOR | \
64 #ifndef CONFIG_CMD_EXT2
65 #define CONFIG_CMD_EXT2
67 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
68 #define CONFIG_SYS_SCSI_MAX_LUN 1
69 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
70 CONFIG_SYS_SCSI_MAX_LUN)
71 #define SCSI_VEND_ID 0x1b4b
72 #define SCSI_DEV_ID 0x9170
73 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
74 #define CONFIG_SCSI_AHCI_PLAT
75 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
77 #endif /* __LS1028A_RDB_H */