1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2020 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #define CONFIG_REMAKE_ELF
12 #include <asm/arch/stream_id_lsch3.h>
13 #include <asm/arch/config.h>
14 #include <asm/arch/soc.h>
16 /* Link Definitions */
17 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_VERY_BIG_RAM
22 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
25 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
26 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
31 #define CPU_RELEASE_ADDR secondary_boot_func
33 /* Generic Timer Definitions */
34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
36 /* Size of malloc() pool */
37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
41 #define CONFIG_SYS_I2C
45 #define CONFIG_SYS_NS16550_SERIAL
46 #define CONFIG_SYS_NS16550_REG_SIZE 1
47 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
49 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
51 /* Miscellaneous configurable options */
52 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
54 /* Physical Memory Map */
55 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
57 #define CONFIG_HWCONFIG
58 #define HWCONFIG_BUFFER_SIZE 128
60 /* Allow to overwrite serial and ethaddr */
61 #define CONFIG_ENV_OVERWRITE
63 #define BOOT_TARGET_DEVICES(func) \
68 #include <config_distro_bootcmd.h>
70 #undef CONFIG_BOOTCOMMAND
72 #define XSPI_NOR_BOOTCOMMAND \
73 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
74 "env exists secureboot && esbc_halt;;"
75 #define SD_BOOTCOMMAND \
76 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
77 "env exists secureboot && esbc_halt;"
78 #define SD2_BOOTCOMMAND \
79 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
80 "env exists secureboot && esbc_halt;"
82 /* Monitor Command Prompt */
83 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
85 sizeof(CONFIG_SYS_PROMPT) + 16)
86 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
88 #define CONFIG_SYS_MAXARGS 64 /* max command args */
90 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
94 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
97 #define CONFIG_SYS_MMC_ENV_DEV 0
98 #define OCRAM_NONSECURE_SIZE 0x00010000
99 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
103 /* I2C bus multiplexer */
104 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
105 #define I2C_MUX_CH_DEFAULT 0x8
108 #define CONFIG_ID_EEPROM
109 #define CONFIG_SYS_I2C_EEPROM_NXID
110 #define CONFIG_SYS_EEPROM_BUS_NUM 0
111 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
117 #define DP_PWD_EN_DEFAULT_MASK 0x8
119 #ifdef CONFIG_NXP_ESBC
120 #include <asm/fsl_secure_boot.h>
124 /* smallest ENETC BD ring has 8 entries */
125 #define CONFIG_SYS_RX_ETH_BUFFER 8
127 #endif /* __L1028A_COMMON_H */