1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2021 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #include <asm/arch/stream_id_lsch3.h>
10 #include <asm/arch/config.h>
11 #include <asm/arch/soc.h>
13 /* Link Definitions */
15 #define CONFIG_VERY_BIG_RAM
16 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
17 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
18 #define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
19 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
24 #define CPU_RELEASE_ADDR secondary_boot_addr
31 #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
33 /* Miscellaneous configurable options */
35 /* Physical Memory Map */
37 #define CONFIG_HWCONFIG
38 #define HWCONFIG_BUFFER_SIZE 128
40 #define BOOT_TARGET_DEVICES(func) \
45 #include <config_distro_bootcmd.h>
47 #define XSPI_NOR_BOOTCOMMAND \
48 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
49 "env exists secureboot && esbc_halt;;"
50 #define SD_BOOTCOMMAND \
51 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
52 "env exists secureboot && esbc_halt;"
53 #define SD2_BOOTCOMMAND \
54 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
55 "env exists secureboot && esbc_halt;"
57 #define OCRAM_NONSECURE_SIZE 0x00010000
58 #define CFG_SYS_FSL_QSPI_BASE 0x20000000
60 /* I2C bus multiplexer */
61 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
62 #define I2C_MUX_CH_DEFAULT 0x8
65 #define DP_PWD_EN_DEFAULT_MASK 0x8
67 #ifdef CONFIG_NXP_ESBC
68 #include <asm/fsl_secure_boot.h>
71 #endif /* __L1028A_COMMON_H */