1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #define CONFIG_REMAKE_ELF
10 #define CONFIG_FSL_LAYERSCAPE
13 #include <asm/arch/stream_id_lsch3.h>
14 #include <asm/arch/config.h>
15 #include <asm/arch/soc.h>
17 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #define CONFIG_VERY_BIG_RAM
23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
24 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
27 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
29 #define CONFIG_CMD_MEMTEST
30 #define CONFIG_SYS_MEMTEST_START 0x80000000
31 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
36 #define CPU_RELEASE_ADDR secondary_boot_func
38 /* Generic Timer Definitions */
39 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
41 /* Size of malloc() pool */
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
46 #define CONFIG_SYS_I2C
50 #define CONFIG_CONS_INDEX 1
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE 1
53 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
55 #define CONFIG_BAUDRATE 115200
56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
58 /* Miscellaneous configurable options */
59 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
61 /* Physical Memory Map */
62 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
64 #define CONFIG_HWCONFIG
65 #define HWCONFIG_BUFFER_SIZE 128
67 /* Allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
70 #define BOOT_TARGET_DEVICES(func) \
74 #include <config_distro_bootcmd.h>
76 /* Initial environment variables */
77 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "board=ls1028ardb\0" \
79 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
80 "ramdisk_addr=0x800000\0" \
81 "ramdisk_size=0x2000000\0" \
82 "fdt_high=0xffffffffffffffff\0" \
83 "initrd_high=0xffffffffffffffff\0" \
84 "fdt_addr=0x00f00000\0" \
85 "kernel_addr=0x01000000\0" \
86 "scriptaddr=0x80000000\0" \
87 "scripthdraddr=0x80080000\0" \
88 "fdtheader_addr_r=0x80100000\0" \
89 "kernelheader_addr_r=0x80200000\0" \
90 "load_addr=0xa0000000\0" \
91 "kernel_addr_r=0x81000000\0" \
92 "fdt_addr_r=0x90000000\0" \
93 "ramdisk_addr_r=0xa0000000\0" \
94 "kernel_start=0x1000000\0" \
95 "kernelheader_start=0x800000\0" \
96 "kernel_load=0xa0000000\0" \
97 "kernel_size=0x2800000\0" \
98 "kernelheader_size=0x40000\0" \
99 "kernel_addr_sd=0x8000\0" \
100 "kernel_size_sd=0x14000\0" \
101 "kernelhdr_addr_sd=0x4000\0" \
102 "kernelhdr_size_sd=0x10\0" \
103 "console=ttyS0,115200\0" \
104 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
106 "boot_scripts=ls1028ardb_boot.scr\0" \
107 "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
108 "scan_dev_for_boot_part=" \
109 "part list ${devtype} ${devnum} devplist; " \
110 "env exists devplist || setenv devplist 1; " \
111 "for distro_bootpart in ${devplist}; do " \
112 "if fstype ${devtype} " \
113 "${devnum}:${distro_bootpart} " \
114 "bootfstype; then " \
115 "run scan_dev_for_boot; " \
118 "scan_dev_for_boot=" \
119 "echo Scanning ${devtype} " \
120 "${devnum}:${distro_bootpart}...; " \
121 "for prefix in ${boot_prefixes}; do " \
122 "run scan_dev_for_scripts; " \
126 "load ${devtype} ${devnum}:${distro_bootpart} " \
127 "${scriptaddr} ${prefix}${script}; " \
128 "env exists secureboot && load ${devtype} " \
129 "${devnum}:${distro_bootpart} " \
130 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
131 "&& esbc_validate ${scripthdraddr};" \
132 "source ${scriptaddr}\0" \
133 "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
134 "sf probe 0:0 && sf read $load_addr " \
135 "$kernel_start $kernel_size ; env exists secureboot &&" \
136 "sf read $kernelheader_addr_r $kernelheader_start " \
137 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
138 " bootm $load_addr#$board\0" \
139 "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
140 "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
141 "&& hdp load $load_addr 0x2000\0" \
142 "sd_bootcmd=echo Trying load from SD ...;" \
143 "mmcinfo; mmc read $load_addr " \
144 "$kernel_addr_sd $kernel_size_sd && " \
145 "env exists secureboot && mmc read $kernelheader_addr_r " \
146 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
147 " && esbc_validate ${kernelheader_addr_r};" \
148 "bootm $load_addr#$board\0" \
149 "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
150 "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
151 "&& hdp load $load_addr 0x2000\0" \
152 "emmc_bootcmd=echo Trying load from EMMC ..;" \
153 "mmcinfo; mmc dev 1; mmc read $load_addr " \
154 "$kernel_addr_sd $kernel_size_sd && " \
155 "env exists secureboot && mmc read $kernelheader_addr_r " \
156 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
157 " && esbc_validate ${kernelheader_addr_r};" \
158 "bootm $load_addr#$board\0" \
159 "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
160 "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
161 "&& hdp load $load_addr 0x2000\0"
163 #undef CONFIG_BOOTCOMMAND
165 #define XSPI_NOR_BOOTCOMMAND \
166 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
167 "env exists secureboot && esbc_halt;;"
168 #define SD_BOOTCOMMAND \
169 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
170 "env exists secureboot && esbc_halt;"
171 #define SD2_BOOTCOMMAND \
172 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
173 "env exists secureboot && esbc_halt;"
175 /* Monitor Command Prompt */
176 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
177 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
178 sizeof(CONFIG_SYS_PROMPT) + 16)
179 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
181 #ifndef CONFIG_CMDLINE_EDITING
182 #define CONFIG_CMDLINE_EDITING 1
185 #define CONFIG_SYS_MAXARGS 64 /* max command args */
187 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
191 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
194 #define CONFIG_SYS_MMC_ENV_DEV 0
195 #define OCRAM_NONSECURE_SIZE 0x00010000
196 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
198 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
200 /* I2C bus multiplexer */
201 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
202 #define I2C_MUX_CH_DEFAULT 0x8
205 #define CONFIG_ID_EEPROM
206 #define CONFIG_SYS_I2C_EEPROM_NXID
207 #define CONFIG_SYS_EEPROM_BUS_NUM 0
208 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
210 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
214 #define DP_PWD_EN_DEFAULT_MASK 0x8
216 #ifdef CONFIG_NXP_ESBC
217 #include <asm/fsl_secure_boot.h>
221 /* smallest ENETC BD ring has 8 entries */
222 #define CONFIG_SYS_RX_ETH_BUFFER 8
224 #endif /* __L1028A_COMMON_H */