1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2021 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #include <asm/arch/stream_id_lsch3.h>
10 #include <asm/arch/config.h>
11 #include <asm/arch/soc.h>
13 /* Link Definitions */
14 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
16 #define CONFIG_VERY_BIG_RAM
17 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
18 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
19 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
20 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
21 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
26 #define CPU_RELEASE_ADDR secondary_boot_addr
33 #define CONFIG_SYS_NS16550_SERIAL
34 #define CONFIG_SYS_NS16550_REG_SIZE 1
35 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
37 /* Miscellaneous configurable options */
39 /* Physical Memory Map */
41 #define CONFIG_HWCONFIG
42 #define HWCONFIG_BUFFER_SIZE 128
44 #define BOOT_TARGET_DEVICES(func) \
49 #include <config_distro_bootcmd.h>
51 #define XSPI_NOR_BOOTCOMMAND \
52 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
53 "env exists secureboot && esbc_halt;;"
54 #define SD_BOOTCOMMAND \
55 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
56 "env exists secureboot && esbc_halt;"
57 #define SD2_BOOTCOMMAND \
58 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
59 "env exists secureboot && esbc_halt;"
61 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
63 #define OCRAM_NONSECURE_SIZE 0x00010000
64 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
66 /* I2C bus multiplexer */
67 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
68 #define I2C_MUX_CH_DEFAULT 0x8
71 #define CONFIG_SYS_I2C_EEPROM_NXID
72 #define CONFIG_SYS_EEPROM_BUS_NUM 0
75 #define DP_PWD_EN_DEFAULT_MASK 0x8
77 #ifdef CONFIG_NXP_ESBC
78 #include <asm/fsl_secure_boot.h>
81 #endif /* __L1028A_COMMON_H */