1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2021 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #define CONFIG_REMAKE_ELF
12 #include <asm/arch/stream_id_lsch3.h>
13 #include <asm/arch/config.h>
14 #include <asm/arch/soc.h>
16 /* Link Definitions */
17 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19 #define CONFIG_VERY_BIG_RAM
20 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
21 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
22 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
23 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
24 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
29 #define CPU_RELEASE_ADDR secondary_boot_addr
31 /* Generic Timer Definitions */
32 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
36 #ifndef CONFIG_MPC8XXX_GPIO
37 #define CONFIG_MPC8XXX_GPIO
44 #define CONFIG_SYS_NS16550_SERIAL
45 #define CONFIG_SYS_NS16550_REG_SIZE 1
46 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
50 /* Miscellaneous configurable options */
52 /* Physical Memory Map */
53 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
55 #define CONFIG_HWCONFIG
56 #define HWCONFIG_BUFFER_SIZE 128
58 #define BOOT_TARGET_DEVICES(func) \
63 #include <config_distro_bootcmd.h>
65 #undef CONFIG_BOOTCOMMAND
67 #define XSPI_NOR_BOOTCOMMAND \
68 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
69 "env exists secureboot && esbc_halt;;"
70 #define SD_BOOTCOMMAND \
71 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
72 "env exists secureboot && esbc_halt;"
73 #define SD2_BOOTCOMMAND \
74 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
75 "env exists secureboot && esbc_halt;"
77 /* Monitor Command Prompt */
78 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
79 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
80 sizeof(CONFIG_SYS_PROMPT) + 16)
81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
83 #define CONFIG_SYS_MAXARGS 64 /* max command args */
85 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
87 #define OCRAM_NONSECURE_SIZE 0x00010000
88 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
92 /* I2C bus multiplexer */
93 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
94 #define I2C_MUX_CH_DEFAULT 0x8
97 #define CONFIG_SYS_I2C_EEPROM_NXID
98 #define CONFIG_SYS_EEPROM_BUS_NUM 0
101 #define DP_PWD_EN_DEFAULT_MASK 0x8
103 #ifdef CONFIG_NXP_ESBC
104 #include <asm/fsl_secure_boot.h>
108 /* smallest ENETC BD ring has 8 entries */
109 #define CONFIG_SYS_RX_ETH_BUFFER 8
111 #endif /* __L1028A_COMMON_H */