1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2021 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #include <asm/arch/stream_id_lsch3.h>
10 #include <asm/arch/config.h>
11 #include <asm/arch/soc.h>
13 /* Link Definitions */
15 #define CONFIG_VERY_BIG_RAM
16 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
17 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
18 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
19 #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
24 #define CPU_RELEASE_ADDR secondary_boot_addr
31 #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
33 /* Miscellaneous configurable options */
35 /* Physical Memory Map */
37 #define HWCONFIG_BUFFER_SIZE 128
39 #define BOOT_TARGET_DEVICES(func) \
44 #include <config_distro_bootcmd.h>
46 #define XSPI_NOR_BOOTCOMMAND \
47 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
48 "env exists secureboot && esbc_halt;;"
49 #define SD_BOOTCOMMAND \
50 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
51 "env exists secureboot && esbc_halt;"
52 #define SD2_BOOTCOMMAND \
53 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
54 "env exists secureboot && esbc_halt;"
56 #define OCRAM_NONSECURE_SIZE 0x00010000
57 #define CFG_SYS_FSL_QSPI_BASE 0x20000000
59 /* I2C bus multiplexer */
60 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
61 #define I2C_MUX_CH_DEFAULT 0x8
64 #define DP_PWD_EN_DEFAULT_MASK 0x8
66 #ifdef CONFIG_NXP_ESBC
67 #include <asm/fsl_secure_boot.h>
70 #endif /* __L1028A_COMMON_H */