1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2020 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #define CONFIG_REMAKE_ELF
10 #define CONFIG_FSL_LAYERSCAPE
13 #include <asm/arch/stream_id_lsch3.h>
14 #include <asm/arch/config.h>
15 #include <asm/arch/soc.h>
17 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #define CONFIG_VERY_BIG_RAM
23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
24 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
27 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
32 #define CPU_RELEASE_ADDR secondary_boot_func
34 /* Generic Timer Definitions */
35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
37 /* Size of malloc() pool */
38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
42 #define CONFIG_SYS_I2C
46 #define CONFIG_CONS_INDEX 1
47 #define CONFIG_SYS_NS16550_SERIAL
48 #define CONFIG_SYS_NS16550_REG_SIZE 1
49 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
51 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
53 /* Miscellaneous configurable options */
54 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
56 /* Physical Memory Map */
57 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
59 #define CONFIG_HWCONFIG
60 #define HWCONFIG_BUFFER_SIZE 128
62 /* Allow to overwrite serial and ethaddr */
63 #define CONFIG_ENV_OVERWRITE
65 #define BOOT_TARGET_DEVICES(func) \
70 #include <config_distro_bootcmd.h>
72 #undef CONFIG_BOOTCOMMAND
74 #define XSPI_NOR_BOOTCOMMAND \
75 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
76 "env exists secureboot && esbc_halt;;"
77 #define SD_BOOTCOMMAND \
78 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
79 "env exists secureboot && esbc_halt;"
80 #define SD2_BOOTCOMMAND \
81 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
82 "env exists secureboot && esbc_halt;"
84 /* Monitor Command Prompt */
85 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
86 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
87 sizeof(CONFIG_SYS_PROMPT) + 16)
88 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
90 #ifndef CONFIG_CMDLINE_EDITING
91 #define CONFIG_CMDLINE_EDITING 1
94 #define CONFIG_SYS_MAXARGS 64 /* max command args */
96 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
100 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
103 #define CONFIG_SYS_MMC_ENV_DEV 0
104 #define OCRAM_NONSECURE_SIZE 0x00010000
105 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
109 /* I2C bus multiplexer */
110 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
111 #define I2C_MUX_CH_DEFAULT 0x8
114 #define CONFIG_ID_EEPROM
115 #define CONFIG_SYS_I2C_EEPROM_NXID
116 #define CONFIG_SYS_EEPROM_BUS_NUM 0
117 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
119 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
123 #define DP_PWD_EN_DEFAULT_MASK 0x8
125 #ifdef CONFIG_NXP_ESBC
126 #include <asm/fsl_secure_boot.h>
130 /* smallest ENETC BD ring has 8 entries */
131 #define CONFIG_SYS_RX_ETH_BUFFER 8
133 #endif /* __L1028A_COMMON_H */