1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2019-2021 NXP
6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H
9 #include <asm/arch/stream_id_lsch3.h>
10 #include <asm/arch/config.h>
11 #include <asm/arch/soc.h>
13 /* Link Definitions */
15 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
16 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
17 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
18 #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
23 #define CPU_RELEASE_ADDR secondary_boot_addr
30 #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
32 /* Miscellaneous configurable options */
34 /* Physical Memory Map */
36 #define HWCONFIG_BUFFER_SIZE 128
38 #define BOOT_TARGET_DEVICES(func) \
43 #include <config_distro_bootcmd.h>
45 #define XSPI_NOR_BOOTCOMMAND \
46 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
47 "env exists secureboot && esbc_halt;;"
48 #define SD_BOOTCOMMAND \
49 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
50 "env exists secureboot && esbc_halt;"
51 #define SD2_BOOTCOMMAND \
52 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
53 "env exists secureboot && esbc_halt;"
55 #define OCRAM_NONSECURE_SIZE 0x00010000
56 #define CFG_SYS_FSL_QSPI_BASE 0x20000000
58 /* I2C bus multiplexer */
59 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
60 #define I2C_MUX_CH_DEFAULT 0x8
63 #define DP_PWD_EN_DEFAULT_MASK 0x8
65 #ifdef CONFIG_NXP_ESBC
66 #include <asm/fsl_secure_boot.h>
69 #endif /* __L1028A_COMMON_H */