include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI
  13 #define CONFIG_ARMV7_PSCI_NR_CPUS       CONFIG_MAX_CPUS
  14
  15 #define CONFIG_SYS_FSL_CLK
  16
  17 #define CONFIG_DISPLAY_CPUINFO
  18 #define CONFIG_DISPLAY_BOARDINFO
  19
  20 #define CONFIG_SKIP_LOWLEVEL_INIT
  21 #define CONFIG_BOARD_EARLY_INIT_F
  22 #define CONFIG_DEEP_SLEEP
  23 #ifdef CONFIG_DEEP_SLEEP
  24 #define CONFIG_SILENT_CONSOLE
  25 #endif
  26
  27 /*
  28  * Size of malloc() pool
  29  */
  30 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  31
  32 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  33 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  34
  35 /*
  36  * USB
  37  */
  38
  39 /*
  40  * EHCI Support - disbaled by default as
  41  * there is no signal coming out of soc on
  42  * this board for this controller. However,
  43  * the silicon still has this controller,
  44  * and anyone can use this controller by
  45  * taking signals out on their board.
  46  */
  47
  48 /*#define CONFIG_HAS_FSL_DR_USB*/
  49
  50 #ifdef CONFIG_HAS_FSL_DR_USB
  51 #define CONFIG_USB_EHCI
  52 #define CONFIG_USB_EHCI_FSL
  53 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  54 #endif
  55
  56 /* XHCI Support - enabled by default */
  57 #define CONFIG_HAS_FSL_XHCI_USB
  58
  59 #ifdef CONFIG_HAS_FSL_XHCI_USB
  60 #define CONFIG_USB_XHCI_FSL
  61 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
  62 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
  63 #endif
  64
  65 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
  66 #define CONFIG_USB_STORAGE
  67 #endif
  68
  69 /*
  70  * Generic Timer Definitions
  71  */
  72 #define GENERIC_TIMER_CLK               12500000
  73
  74 #define CONFIG_SYS_CLK_FREQ             100000000
  75 #define CONFIG_DDR_CLK_FREQ             100000000
  76
  77 #define DDR_SDRAM_CFG                   0x470c0008
  78 #define DDR_CS0_BNDS                    0x008000bf
  79 #define DDR_CS0_CONFIG                  0x80014302
  80 #define DDR_TIMING_CFG_0                0x50550004
  81 #define DDR_TIMING_CFG_1                0xbcb38c56
  82 #define DDR_TIMING_CFG_2                0x0040d120
  83 #define DDR_TIMING_CFG_3                0x010e1000
  84 #define DDR_TIMING_CFG_4                0x00000001
  85 #define DDR_TIMING_CFG_5                0x03401400
  86 #define DDR_SDRAM_CFG_2                 0x00401010
  87 #define DDR_SDRAM_MODE                  0x00061c60
  88 #define DDR_SDRAM_MODE_2                0x00180000
  89 #define DDR_SDRAM_INTERVAL              0x18600618
  90 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  91 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  92 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  93 #define DDR_DDR_CDR1                    0x80040000
  94 #define DDR_DDR_CDR2                    0x00000001
  95 #define DDR_SDRAM_CLK_CNTL              0x02000000
  96 #define DDR_DDR_ZQ_CNTL                 0x89080600
  97 #define DDR_CS0_CONFIG_2                0
  98 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  99 #define SDRAM_CFG2_D_INIT               0x00000010
 100 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
 101 #define SDRAM_CFG2_FRC_SR               0x80000000
 102 #define SDRAM_CFG_BI                    0x00000001
 103
 104 #ifdef CONFIG_RAMBOOT_PBL
 105 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
 106 #endif
 107
 108 #ifdef CONFIG_SD_BOOT
 109 #ifdef CONFIG_SD_BOOT_QSPI
 110 #define CONFIG_SYS_FSL_PBL_RCW  \
 111         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
 112 #else
 113 #define CONFIG_SYS_FSL_PBL_RCW  \
 114         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
 115 #endif
 116 #define CONFIG_SPL_FRAMEWORK
 117 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 118 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 119 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 120 #define CONFIG_SPL_ENV_SUPPORT
 121 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 122 #define CONFIG_SPL_I2C_SUPPORT
 123 #define CONFIG_SPL_WATCHDOG_SUPPORT
 124 #define CONFIG_SPL_SERIAL_SUPPORT
 125 #define CONFIG_SPL_MMC_SUPPORT
 126 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
 127
 128 #ifdef CONFIG_SECURE_BOOT
 129 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 130 /*
 131  * HDR would be appended at end of image and copied to DDR along
 132  * with U-Boot image.
 133  */
 134 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              (0x400 + \
 135                 (CONFIG_U_BOOT_HDR_SIZE / 512)
 136 #else
 137 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
 138 #endif /* ifdef CONFIG_SECURE_BOOT */
 139
 140 #define CONFIG_SPL_TEXT_BASE            0x10000000
 141 #define CONFIG_SPL_MAX_SIZE             0x1a000
 142 #define CONFIG_SPL_STACK                0x1001d000
 143 #define CONFIG_SPL_PAD_TO               0x1c000
 144 #define CONFIG_SYS_TEXT_BASE            0x82000000
 145
 146 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 147                 CONFIG_SYS_MONITOR_LEN)
 148 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 149 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 150 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 151
 152 #ifdef CONFIG_U_BOOT_HDR_SIZE
 153 /*
 154  * HDR would be appended at end of image and copied to DDR along
 155  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 156  * size increases then increase this size in case of secure boot as
 157  * it uses raw u-boot image instead of fit image.
 158  */
 159 #define CONFIG_SYS_MONITOR_LEN          (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
 160 #else
 161 #define CONFIG_SYS_MONITOR_LEN          0x80000
 162 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 163 #endif
 164
 165 #ifdef CONFIG_QSPI_BOOT
 166 #define CONFIG_SYS_TEXT_BASE            0x40010000
 167 #endif
 168
 169 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 170 #define CONFIG_SYS_NO_FLASH
 171 #endif
 172
 173 #ifndef CONFIG_SYS_TEXT_BASE
 174 #define CONFIG_SYS_TEXT_BASE            0x60100000
 175 #endif
 176
 177 #define CONFIG_NR_DRAM_BANKS            1
 178 #define PHYS_SDRAM                      0x80000000
 179 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 180
 181 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 182 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 183
 184 #define CONFIG_SYS_HAS_SERDES
 185
 186 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 187
 188 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 189         !defined(CONFIG_QSPI_BOOT)
 190 #define CONFIG_U_QE
 191 #endif
 192
 193 /*
 194  * IFC Definitions
 195  */
 196 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 197 #define CONFIG_FSL_IFC
 198 #define CONFIG_SYS_FLASH_BASE           0x60000000
 199 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 200
 201 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 202 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 203                                 CSPR_PORT_SIZE_16 | \
 204                                 CSPR_MSEL_NOR | \
 205                                 CSPR_V)
 206 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 207
 208 /* NOR Flash Timing Params */
 209 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 210                                         CSOR_NOR_TRHZ_80)
 211 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 212                                         FTIM0_NOR_TEADC(0x5) | \
 213                                         FTIM0_NOR_TAVDS(0x0) | \
 214                                         FTIM0_NOR_TEAHC(0x5))
 215 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 216                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 217                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 218 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 219                                         FTIM2_NOR_TCH(0x4) | \
 220                                         FTIM2_NOR_TWP(0x1c) | \
 221                                         FTIM2_NOR_TWPH(0x0e))
 222 #define CONFIG_SYS_NOR_FTIM3            0
 223
 224 #define CONFIG_FLASH_CFI_DRIVER
 225 #define CONFIG_SYS_FLASH_CFI
 226 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 227 #define CONFIG_SYS_FLASH_QUIET_TEST
 228 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 229
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 234
 235 #define CONFIG_SYS_FLASH_EMPTY_INFO
 236 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 237
 238 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 239 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 240 #endif
 241
 242 /* CPLD */
 243
 244 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 245 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 246
 247 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 248 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 249                                         CSPR_PORT_SIZE_8 | \
 250                                         CSPR_MSEL_GPCM | \
 251                                         CSPR_V)
 252 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 253 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 254                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 255                                         CSOR_NOR_TRHZ_80)
 256
 257 /* CPLD Timing parameters for IFC GPCM */
 258 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 259                                         FTIM0_GPCM_TEADC(0xf) | \
 260                                         FTIM0_GPCM_TEAHC(0xf))
 261 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 262                                         FTIM1_GPCM_TRAD(0x3f))
 263 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 264                                         FTIM2_GPCM_TCH(0xf) | \
 265                                         FTIM2_GPCM_TWP(0xff))
 266 #define CONFIG_SYS_FPGA_FTIM3           0x0
 267 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 268 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 269 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 270 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 271 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 272 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 273 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 274 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 275 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 276 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 277 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 278 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 279 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 280 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 281 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 282 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 283
 284 /*
 285  * Serial Port
 286  */
 287 #ifdef CONFIG_LPUART
 288 #define CONFIG_LPUART_32B_REG
 289 #else
 290 #define CONFIG_CONS_INDEX               1
 291 #define CONFIG_SYS_NS16550_SERIAL
 292 #ifndef CONFIG_DM_SERIAL
 293 #define CONFIG_SYS_NS16550_REG_SIZE     1
 294 #endif
 295 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 296 #endif
 297
 298 #define CONFIG_BAUDRATE                 115200
 299
 300 /*
 301  * I2C
 302  */
 303 #define CONFIG_SYS_I2C
 304 #define CONFIG_SYS_I2C_MXC
 305 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 306 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 307 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 308
 309 /* EEPROM */
 310 #define CONFIG_ID_EEPROM
 311 #define CONFIG_SYS_I2C_EEPROM_NXID
 312 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 313 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 314 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 317
 318 /*
 319  * MMC
 320  */
 321 #define CONFIG_MMC
 322 #define CONFIG_FSL_ESDHC
 323 #define CONFIG_GENERIC_MMC
 324
 325 #define CONFIG_DOS_PARTITION
 326
 327 /* SPI */
 328 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 329 /* QSPI */
 330 #define QSPI0_AMBA_BASE                 0x40000000
 331 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 332 #define FSL_QSPI_FLASH_NUM              2
 333
 334 /* DSPI */
 335 #endif
 336
 337 /* DM SPI */
 338 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 339 #define CONFIG_DM_SPI_FLASH
 340 #endif
 341
 342 /*
 343  * Video
 344  */
 345 #define CONFIG_FSL_DCU_FB
 346
 347 #ifdef CONFIG_FSL_DCU_FB
 348 #define CONFIG_VIDEO
 349 #define CONFIG_CMD_BMP
 350 #define CONFIG_CFB_CONSOLE
 351 #define CONFIG_VGA_AS_SINGLE_DEVICE
 352 #define CONFIG_VIDEO_LOGO
 353 #define CONFIG_VIDEO_BMP_LOGO
 354 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 355
 356 #define CONFIG_FSL_DCU_SII9022A
 357 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 358 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 359 #endif
 360
 361 /*
 362  * eTSEC
 363  */
 364 #define CONFIG_TSEC_ENET
 365
 366 #ifdef CONFIG_TSEC_ENET
 367 #define CONFIG_MII
 368 #define CONFIG_MII_DEFAULT_TSEC         1
 369 #define CONFIG_TSEC1                    1
 370 #define CONFIG_TSEC1_NAME               "eTSEC1"
 371 #define CONFIG_TSEC2                    1
 372 #define CONFIG_TSEC2_NAME               "eTSEC2"
 373 #define CONFIG_TSEC3                    1
 374 #define CONFIG_TSEC3_NAME               "eTSEC3"
 375
 376 #define TSEC1_PHY_ADDR                  2
 377 #define TSEC2_PHY_ADDR                  0
 378 #define TSEC3_PHY_ADDR                  1
 379
 380 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 381 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 382 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 383
 384 #define TSEC1_PHYIDX                    0
 385 #define TSEC2_PHYIDX                    0
 386 #define TSEC3_PHYIDX                    0
 387
 388 #define CONFIG_ETHPRIME                 "eTSEC1"
 389
 390 #define CONFIG_PHY_GIGE
 391 #define CONFIG_PHYLIB
 392 #define CONFIG_PHY_ATHEROS
 393
 394 #define CONFIG_HAS_ETH0
 395 #define CONFIG_HAS_ETH1
 396 #define CONFIG_HAS_ETH2
 397 #endif
 398
 399 /* PCIe */
 400 #define CONFIG_PCI              /* Enable PCI/PCIE */
 401 #define CONFIG_PCIE1            /* PCIE controller 1 */
 402 #define CONFIG_PCIE2            /* PCIE controller 2 */
 403 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 404 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 405
 406 #define CONFIG_SYS_PCI_64BIT
 407
 408 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 409 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 410 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 411 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 412
 413 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 414 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 415 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 416
 417 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 418 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 419 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 420
 421 #ifdef CONFIG_PCI
 422 #define CONFIG_PCI_PNP
 423 #define CONFIG_PCI_SCAN_SHOW
 424 #define CONFIG_CMD_PCI
 425 #endif
 426
 427 #define CONFIG_CMDLINE_TAG
 428 #define CONFIG_CMDLINE_EDITING
 429
 430 #define CONFIG_ARMV7_NONSEC
 431 #define CONFIG_ARMV7_VIRT
 432 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 433 #define CONFIG_LAYERSCAPE_NS_ACCESS
 434 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 435 #define CONFIG_TIMER_CLK_FREQ           12500000
 436
 437 #define CONFIG_HWCONFIG
 438 #define HWCONFIG_BUFFER_SIZE            256
 439
 440 #define CONFIG_FSL_DEVICE_DISABLE
 441
 442
 443 #ifdef CONFIG_LPUART
 444 #define CONFIG_EXTRA_ENV_SETTINGS       \
 445         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 446         "initrd_high=0xffffffff\0"      \
 447         "fdt_high=0xffffffff\0"
 448 #else
 449 #define CONFIG_EXTRA_ENV_SETTINGS       \
 450         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 451         "initrd_high=0xffffffff\0"      \
 452         "fdt_high=0xffffffff\0"
 453 #endif
 454
 455 /*
 456  * Miscellaneous configurable options
 457  */
 458 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 459 #define CONFIG_AUTO_COMPLETE
 460 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 461 #define CONFIG_SYS_PBSIZE               \
 462                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 463 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 464 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 465
 466 #define CONFIG_SYS_MEMTEST_START        0x80000000
 467 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 468
 469 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 470
 471 #define CONFIG_LS102XA_STREAM_ID
 472
 473 /*
 474  * Stack sizes
 475  * The stack sizes are set up in start.S using the settings below
 476  */
 477 #define CONFIG_STACKSIZE                (30 * 1024)
 478
 479 #define CONFIG_SYS_INIT_SP_OFFSET \
 480         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 481 #define CONFIG_SYS_INIT_SP_ADDR \
 482         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 483
 484 #ifdef CONFIG_SPL_BUILD
 485 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 486 #else
 487 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 488 #endif
 489
 490 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 491
 492 /*
 493  * Environment
 494  */
 495 #define CONFIG_ENV_OVERWRITE
 496
 497 #if defined(CONFIG_SD_BOOT)
 498 #define CONFIG_ENV_OFFSET               0x100000
 499 #define CONFIG_ENV_IS_IN_MMC
 500 #define CONFIG_SYS_MMC_ENV_DEV          0
 501 #define CONFIG_ENV_SIZE                 0x20000
 502 #elif defined(CONFIG_QSPI_BOOT)
 503 #define CONFIG_ENV_IS_IN_SPI_FLASH
 504 #define CONFIG_ENV_SIZE                 0x2000
 505 #define CONFIG_ENV_OFFSET               0x100000
 506 #define CONFIG_ENV_SECT_SIZE            0x10000
 507 #else
 508 #define CONFIG_ENV_IS_IN_FLASH
 509 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 510 #define CONFIG_ENV_SIZE                 0x20000
 511 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 512 #endif
 513
 514 #define CONFIG_MISC_INIT_R
 515
 516 /* Hash command with SHA acceleration supported in hardware */
 517 #ifdef CONFIG_FSL_CAAM
 518 #define CONFIG_CMD_HASH
 519 #define CONFIG_SHA_HW_ACCEL
 520 #endif
 521
 522 #include <asm/fsl_secure_boot.h>
 523 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 524
 525 #endif